Patents by Inventor Sean Eilert

Sean Eilert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
    Publication number: 20150370750
    Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Sean Eilert, Mark Leinwander
  • TRANSACTIONAL MEMORY
    Publication number: 20150347315
    Abstract: Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Inventor: SEAN EILERT
  • Resting blocks of memory cells in response to the blocks being deemed to fail
    Patent number: 9183070
    Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
  • Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
    Patent number: 9165688
    Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Chris Bueb, Sean Eilert
  • Memory device for a hierarchical memory architecture
    Patent number: 9123409
    Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: September 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sean Eilert, Mark Leinwander
  • Transactional memory
    Patent number: 9104690
    Abstract: Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 11, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sean Eilert
  • ERROR CONTROL IN MEMORY STORAGE SYSTEMS
    Publication number: 20150220395
    Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 6, 2015
    Inventors: CHRISTOPHER BUEB, SEAN EILERT
  • AUTONOMOUS MEMORY SUBSYSTEM ARCHITECTURE
    Publication number: 20150205530
    Abstract: An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Sean Eilert, Mark Leinwander, Jared Hulbert
  • METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY
    Publication number: 20150153963
    Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Kenneth M Curewitz, Sean Eilert, Ameen D. Akel, Hongyu Wang
  • Error control in memory storage systems
    Patent number: 9047191
    Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: June 2, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Bueb, Sean Eilert
  • Autonomous memory subsystem architecture
    Patent number: 9015440
    Abstract: An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sean Eilert, Mark Leinwander, Jared Hulbert
  • METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY SEARCHING
    Publication number: 20150052114
    Abstract: Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a FIFO queue and searches can be subsequently generated for each search request. The resulting plurality of searches can be executed substantially in parallel on the database. A respective indication is transmitted to a requesting host when either each respective search is complete or each respective search has generated search results.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Kenneth M. Curewitz, Sean Eilert, Hongyu Wang, Ameen D. Akel
  • RESTING BLOCKS OF MEMORY CELLS IN RESPONSE TO THE BLOCKS BEING DEEMED TO FAIL
    Publication number: 20150033087
    Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
  • APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY
    Publication number: 20140351630
    Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventors: Chris Bueb, Sean Eilert
  • Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
    Patent number: 8806303
    Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chris Bueb, Sean Eilert
  • ERROR CONTROL IN MEMORY STORAGE SYSTEMS
    Publication number: 20140129872
    Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Christopher Bueb, Sean Eilert
  • APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY
    Publication number: 20140047283
    Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 13, 2014
    Applicant: Micron Technology Inc.
    Inventors: Chris Bueb, Sean Eilert
  • Error control in memory storage systems
    Patent number: 8635514
    Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Bueb, Sean Eilert
  • Hierarchical memory architecture to connect mass storage devices
    Patent number: 8621148
    Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Sean Eilert
  • Full chip wear leveling in memory device
    Patent number: 8601202
    Abstract: Methods and systems to wear level a non-volatile memory device across partitions. In an embodiment, a memory device performs background operations to swap host addressable memory partitions with a spare memory partition outside of the host address space. In one embodiment, the background inter-partition wear leveling operations are appended to a user erase operations.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Robert Melcher, Sean Eilert, Gerard Kreifels