Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices.

Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Abstract: A Phase-Change Memory (PCM) Content Addressable Memory (CAM) utilized to store addresses of defective rows or columns of a memory array or memories attached to a backside bus of a concentrator device.

Abstract: Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.

Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.

Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.

Abstract: Subject matter disclosed herein relates to techniques to perform transactions using a memory device.

Abstract: A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device.

Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.

Abstract: Writing to non-volatile memory during a volatile memory refresh cycle is described. In one example, a write command is received and data is received to write into a memory cell. The data is temporarily stored in response to the write command. A refresh command is received and the temporarily stored data is written into the memory cell in response to the refresh command.

Abstract: Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans its memory cells, performing a multi-level read on memory cells in a single bit per cell mode. Depending on the state sensed, the cell is refreshed to a correct state if necessary. In one embodiment, the memory scan is appended to a user erase operation, a flash block is swapped with another bock if the state sensed indicates charge gain, and a flash cell is programmed up if the state sensed indicates charge loss.

Abstract: An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.

Abstract: An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller.

Abstract: A memory and a method of correcting and detecting an error in a codeword of a memory are presented. The method includes detection and correction of an error in a bit of the codeword by an error deception and correction engine, storing error correction information of the error in a cache. In the second detection of the same error in the same bit the correction of the error is done based on the stored error correction information.

Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Abstract: A Phase-Change Memory (PCM) Content Addressable Memory (CAM) utilized to store addresses of defective rows or columns of a memory array or memories attached to a backside bus of a concentrator device.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.