Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide an interface to accommodate different memory formats.

Abstract: Near-Field UHF wireless coupling may be used to write data into a non-volatile memory in a device, thus allowing for changes to be made to the device after that product has been manufactured. Energy from the received wireless signal may be used to power sufficient circuitry in the device so that the programming does not require an on-board power source such as a battery. In many cases, the device may be programmed after it has been packaged for shipment/sale, without removing the device from the package. In some embodiments, a multi-segment antenna may be used to program multiple such devices at the same time by the same Near-Field UHF signal.

Abstract: A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus. One of the interfaces may be a random access memory interface and the second interface may be a paged access interface.

Abstract: A memory and a method of correcting and detecting an error in a codeword of a memory are presented. The method includes detection and correction of an error in a bit of the codeword by an error deception and correction engine, storing error correction information of the error in a cache. In the second detection of the same error in the same bit the correction of the error is done based on the stored error correction information.

Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.

Abstract: A method and apparatus for providing execution resources in a flash device is described herein. In a first mode, a write buffer in the flash device is used as a general purpose memory, i.e. a processing element, such as a host microprocessor uses the write buffer as an execution/variable space. In the first mode the write buffer is mapped as part of the flash address map, which is visible to the processing element for reading and writing. In a second mode, the write buffer acts as a buffer to write data into an array in the flash, as in normal operation. A selection/toggle module is used to select/toggle between the first and second modes. The selection or toggle may be based on commands, instructions, interrupts, user-initiated events, system-initiated events, or any combination thereof.

Abstract: A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus. One of the interfaces may be a random access memory interface and the second interface may be a paged access interface.

Abstract: Provided are a method and device for logging changes to blocks in a non-volatile memory. Security bits are maintained for blocks of cells in a non-volatile memory device indicating whether data in the blocks has been modified. The security bit for one block is set to indicate modification in response to detecting that at least one cell in the block was modified.

Abstract: A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with a higher drain bias and is, therefore, more susceptible to the read disturb problem.

Abstract: A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with a higher drain bias and is, therefore, more susceptible to the read disturb problem.

Abstract: According to some embodiments, power loss recovery information related to an active operation is stored in volatile memory. Upon detection of a power loss condition, the power loss recovery information is copied to non-volatile memory. Upon a return of power, the power loss recovery information is used to complete or correct the interrupted operation.

Abstract: Method and apparatus to perform virtual memory management using a general memory access processor are described.

Abstract: A nonvolatile memory device may include circuitry to support the partitioning of the memory into two or more logical partitions. The two or more logical partitions may be accessible by two or more separate interfaces with different characteristics.

Abstract: A nonvolatile stack configured within a nonvolatile memory.

Abstract: A method for generating a unique device ID for each addressable device in a stack of multiple addressable devices by encoding a device ID for one device in the stack and determining a device ID for each of the other devices based on the device ID of an adjacent device in the stack.