Abstract: The present invention provides a transformer device. In an example, the transformer device has a semiconductor substrate member comprising a first surface and a second surface. In an example, the device has a metal material having a thickness and configured spatially in a pattern to form a distributed transformer device. The pattern has a plurality of primary tracks numbered from 2 to J, where J is an integer from two to forty, and a plurality of secondary tracks numbered from 2 to K, where K is an integer from two to forty. In an example, the plurality of primary tracks and the plurality of secondary tracks are configured collectively to form an electromagnetic field from the plurality of primary tracks to produce a magnetic flux to induce a varying current coupled to the plurality of secondary tracks.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming an additional GND layer on a part of a fan-out packaging substrate, forming a first dielectric layer having a first via hole on the additional GND layer, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the additional GND layer is formed in directions toward four sides or at least two opposite sides of a die.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device, which is a method of manufacturing a packaging device using a wafer or panel level packaging process, the method including forming a first dielectric layer having a first via hole on a fan-out packaging substrate, forming a redistribution layer (RDL) on the first dielectric layer and the first via hole, forming a second dielectric layer having a second via hole formed on the redistribution layer, and forming a bump structure on the second dielectric layer and the second via hole so as to be connected to the redistribution layer, wherein the redistribution layer includes a metal sealing ring to extend a conductor path in a plating process.

Abstract: A data storage and access system for use with a processor having processor cache such that the processor is configured generate a data request for data which is provided to a final level cache (FLC) cache system that is configured to function as main memory and receive the data request. The FLC cache system comprising a first FLC module configured to process the data request from the processor. A second FLC module, responsive to the first FLC module not having the data requested by the processor, receives and processes the data request from the first FLC module. A switch accessible memory, which connects through a switch to the second FLC module, is configured to receive the data request responsive to the second FLC module not having the data. The switch accessible memory may be shared by additional FLC cache systems as a shared memory pool.

Abstract: A cable for use between a host and an external memory. The cable has a first and second ends and two or more electrically conductive conductors, surrounded by an insulator, extending from the first to the second end. At the first end is a first cable connector that is electrically connected to the conductors and physically connected to the insulator. The first cable connector connects to an external memory. A second cable connector, at the second end, is electrically connected to the conductors and physically connected to the insulator. The second cable connector connects to a host. A final level cache (FLC) system, in the second cable connector, comprises a connector memory with associated controller configured to store data, and a FLC controller with memory. The FLC controller stores memory addresses that correspond to data stored in the connector memory and operates the connector memory as a cache memory.

Abstract: A memory system, operating under the HBM standard, comprising a memory stack having layers of memory dies, on a base die. The base die is in communication with the memory stack and further comprises final level cache (FLC) controller. The FLC controller configured to receive the data request for requested data from a requesting element and process the data request to determine if the requested data is stored in the memory stack. Responsive to the requested data being stored in the memory stack, retrieve the requested data from the memory stack, transmit the requested data to the processor, and update a recently used tag associated with the requested data. Responsive to the requested data not being stored in the memory stack, the final level cache controller retrieves the requested data from an external memory, transmits the requested data to the processor, and stores the requested data in the memory stack.

Abstract: An amplifier system comprising an input matching network configured to receive an input signal from a signal source. The input matching network is configured to impedance match between the amplifier system and the signal source. An input transformer is configured to receive the impedance matched input signal and perform voltage step down and current step up. An amplifier is configured to receive and amplify an output signal from the input transformer to generate an amplified signal. A low winding ratio output transformer provides isolation between an antenna and amplifier. An output matching network is configured to impedance match to an antenna and provide voltage step up. The input transformer may have a ratio of 2N:N, such as 2:1 ratio. At least one center tap of the input transformer may connect to a bias voltage. The amplifier system may be configured for operation in the radio frequency band.

Abstract: Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.

Abstract: Apparatus and method to logically process signals representative of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level of the logical processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay. At least one of the bit-representative signals is inverted prior to the input registers or prior to processing by the logical processing stage. The delay is reduced by omitting an inverting function in a carry circuit associated with at least one logical processing stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval.

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Abstract: To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Abstract: A latch for a flip-flop or other circuit which requires fewer signal inputs than prior latch designs to reduce power consumption. The latch comprises a first transistor set is switching element and is configured to receive clock signals from a clock network and an input signal. A second transistor receives the input signal from the first transistor set and is configured as a first data buffer to create a latch output. A feedback path includes a third transistor set in series with a resistor or transistor pair. The feedback path receives the latch output and generates a feedback signal, which is provided to the first transistor set. The resistor or transistor pair is selected to establish the feedback signal at a magnitude that is sufficiently large to maintain the state of the latch but sufficiently small to allow a change in the input signal to change the latch output.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Abstract: A battery and battery balancing system comprising a battery pack comprising two or more cells connected in series and a separate balancing cell, which is not series connected in the battery pack. The balancing cell is configured to be selectively switched into connection with one or more cells of the battery pack. A charging input is configured to accept a charging current from a power source to charge the battery pack. Two or more balancing cell switches, responsive to switch control signals, configured to selectively connect the balancing cell to a cell in the battery pack. A cell monitoring and switch control unit configured to monitor cell parameters during charging and generate the switch control signals, such that upon the monitoring determining that a cell in the battery pack is an underperforming cell, switching the balancing cell into connection with the underperforming cell to supplement the underperforming cell.

Abstract: A noise tolerant buffer circuit, configured to interface a controller to a switching device, that includes an input, a first buffer, a second buffer, an output, and a switching device. The input provides a control signal to the first buffer cell input. The first buffer cell processes the control signal to generate a second buffer output. The second buffer cell processes the output of the first buffer to generate a second buffer output. The switching device is configured to receive an output of the second buffer and perform a switching operation based on the output of the second buffer. The switching operation generates noise that couples back to the first buffer cell and the second buffer cell, and the noise is divided between the first buffer cell and a second buffer to thereby reduce the noise to a value that does not trigger the first buffer or the second buffer.