Patents by Inventor Sehat Sutardja

Sehat Sutardja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210173779
    Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Inventor: Sehat Sutardja
  • Patent number: 10936492
    Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 2, 2021
    Assignee: FLC Technology Group, Inc.
    Inventor: Sehat Sutardja
  • Publication number: 20200301836
    Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 24, 2020
    Inventor: Sehat Sutardja
  • Patent number: 10761737
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 1, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventor: Sehat Sutardja
  • Patent number: 10684949
    Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 16, 2020
    Assignee: FLC Global, Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20200075232
    Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventor: Sehat Sutardja
  • Publication number: 20200075214
    Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventor: Sehat Sutardja
  • Publication number: 20190384709
    Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 19, 2019
    Inventor: Sehat Sutardja
  • Publication number: 20180373442
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventor: Sehat SUTARDJA
  • Publication number: 20180293167
    Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
    Type: Application
    Filed: March 23, 2018
    Publication date: October 11, 2018
    Inventor: Sehat Sutardja
  • Patent number: 10082846
    Abstract: A temperature sensing system includes N temperature sensing circuits, each including a diode, that are connected in series, wherein N is an integer greater than one. A control module includes a first terminal that communicates with one of the N temperature sensing circuits, that receives a combined voltage of the N temperature sensing circuits at the first terminal, and that calculates an average temperature of the N temperature sensing circuits based on the combined voltage.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: September 25, 2018
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 10067687
    Abstract: A storage system includes a final level cache (FLC) module coupled to a storage medium. The storage medium includes a bulk storage portion having a higher data density than a cache storage portion. The cache storage portion is configured as an FLC cache accessed by the FLC module prior to accessing the bulk storage portion. The FLC module receives a request for data from a processor coupled to one or more levels of cache that are separate from the FLC cache. The processor generates the request if the data is not cached in the one or more levels of cache. The FLC module determines whether the data requested is cached in the FLC cache, retrieves the data from the FLC cache if the data is cached in the FLC cache, and retrieves the data from the bulk storage portion if the data is not cached in the FLC cache.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: September 4, 2018
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9961006
    Abstract: A network switch includes a plurality of ports to communicate via a communication channel. Each of the plurality of ports includes an auto-negotiation circuit to negotiate a first data transmission rate with a network device in communication with the network switch via the communication channel, a transceiver circuit to receive, from the network switch, data via the communication channel at the negotiated first data transmission rate, and a transmitter/encoder circuit. The transmitter/encoder circuit is to receive the negotiated first data transmission rate from the auto-negotiation circuit, receive the data from the transceiver circuit, and selectively replicate portions of the data received from the transceiver circuit to transmit the data at a second data transmission rate that is different from the negotiated first data transmission rate.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 1, 2018
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, William Lo
  • Patent number: 9941774
    Abstract: A motor having a rotor, the rotor including a first metal plate having a first size and a second metal plate having a second size arranged on a first surface associated with the rotor. The first metal plate and the second metal plate are arranged adjacent to each other at a predetermined distance from an axis of rotation of the rotor. The first surface rotates perpendicularly about the axis in response to the rotor being rotated about the axis. A stator includes a third metal plate arranged on a second surface associated with the stator. The third metal plate is arranged on the second surface at the predetermined distance from the axis. The second surface is parallel to the first surface and faces the first surface.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: April 10, 2018
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9928172
    Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 27, 2018
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9847291
    Abstract: A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: December 19, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Poh Boon Leong, Hou Xian Loo, Sehat Sutardja, Wei Ding, Huy Thong Nguyen
  • Publication number: 20170344276
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventor: Sehat Sutardja
  • Patent number: 9733841
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: August 15, 2017
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Publication number: 20170177481
    Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 22, 2017
    Inventor: Sehat Sutardja
  • Patent number: 9654066
    Abstract: A system includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to amplify an input signal and generate first output signals. The first amplifier stage includes a common-source differential amplifier. The common-source differential amplifier includes a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) having source terminals connected to a common potential. The second amplifier stage includes a first differential amplifier and a second differential amplifier configured to respectively generate first and second differential outputs based on the first output signals. Each of the first and second differential amplifiers includes a plurality of MOSFETs having source terminals connected to the common potential via a respective balun.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: May 16, 2017
    Assignee: Marvell World Trade LTD.
    Inventors: Poh Boon Leong, Sehat Sutardja