Abstract: To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Abstract: A latch for a flip-flop or other circuit which requires fewer signal inputs than prior latch designs to reduce power consumption. The latch comprises a first transistor set is switching element and is configured to receive clock signals from a clock network and an input signal. A second transistor receives the input signal from the first transistor set and is configured as a first data buffer to create a latch output. A feedback path includes a third transistor set in series with a resistor or transistor pair. The feedback path receives the latch output and generates a feedback signal, which is provided to the first transistor set. The resistor or transistor pair is selected to establish the feedback signal at a magnitude that is sufficiently large to maintain the state of the latch but sufficiently small to allow a change in the input signal to change the latch output.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Abstract: A noise tolerant buffer circuit, configured to interface a controller to a switching device, that includes an input, a first buffer, a second buffer, an output, and a switching device. The input provides a control signal to the first buffer cell input. The first buffer cell processes the control signal to generate a second buffer output. The second buffer cell processes the output of the first buffer to generate a second buffer output. The switching device is configured to receive an output of the second buffer and perform a switching operation based on the output of the second buffer. The switching operation generates noise that couples back to the first buffer cell and the second buffer cell, and the noise is divided between the first buffer cell and a second buffer to thereby reduce the noise to a value that does not trigger the first buffer or the second buffer.

Abstract: A battery and battery balancing system comprising a battery pack comprising two or more cells connected in series and a separate balancing cell, which is not series connected in the battery pack. The balancing cell is configured to be selectively switched into connection with one or more cells of the battery pack. A charging input is configured to accept a charging current from a power source to charge the battery pack. Two or more balancing cell switches, responsive to switch control signals, configured to selectively connect the balancing cell to a cell in the battery pack. A cell monitoring and switch control unit configured to monitor cell parameters during charging and generate the switch control signals, such that upon the monitoring determining that a cell in the battery pack is an underperforming cell, switching the balancing cell into connection with the underperforming cell to supplement the underperforming cell.

Abstract: A transformer comprising a first signal path in a first plane or layer and a second signal path in the same plane or layer. The second signal path is offset in a diagonally direction in relation to the first signal path, such that the first signal path and the second signal path are in proximity to establish electric-field coupling between the first signal path and the second signal path. A jumper, located in a second plane, is electrically connected to either the first signal path or the second signal path through vias that extend from the first plane to the second plane. The jumper prevents electrical contact between the first and the second signal path at locations where the first and the second signal path would otherwise intersect on the first plane. The shape of the first and second signal paths may be square or rectangular, or both.

Abstract: A front-end module, compatible with various baseband chipset configurations, that includes a transmit signal path having a transmit amplifier, to amplify an outgoing signal, and a coupler. The coupler diverts a first portion of the outgoing signal, to a transmit-receive switch, a second portion to a receive path switch, and a third portion to a RF-coupling port. As included is a receive signal path including a low-noise amplifier, configured to receive an incoming signal, and a receive path switch. The receive path switch receives the incoming signal, from the transmit-receive switch, and the second portion of the outgoing signal from the coupler. The receive signal path also includes a receive port configured to selectively receive, through the receive path switch, incoming signals from an antenna and the second portion of the outgoing signal. A RF coupling port connects to the coupler to receive the third portion of the outgoing signal.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Abstract: A data storage and access system for use with a processor having processor cache such that the processor is configured generate a data request for data which is provided to a final level cache (FLC) cache system that is configured to function as main memory and receive the data request. The FLC cache system comprising a first FLC module configured to process the data request from the processor. A second FLC module, responsive to the first FLC module not having the data requested by the processor, receives and processes the data request from the first FLC module. A switch accessible memory, which connects through a switch to the second FLC module, is configured to receive the data request responsive to the second FLC module not having the data. The switch accessible memory may be shared by additional FLC cache systems as a shared memory pool.

Abstract: A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Abstract: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

Abstract: A LNA comprises an input, a transformer structure and a first transistor and a second transistor, each having gate, source, and drain terminals. The transformer structure has a first winding pair, a second winding pair and a third winding pair. Each winding of the first winding pair connects to the input node and one source terminals of the transistors. The second winding pair is proximate the first winding pair. The second winding pair connects to a ground node and the transistor source terminals. The third winding pair is proximate the first winding pair and it connects to a bias signal source and a gate terminal of the transistors. An output connects to the transistor drain terminals. The windings of the first and second winding pairs are offset and rotated 180 degrees with respect to the other winding in the pair. The third winding pair performs a Gm boost function.

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Abstract: To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.