Patents by Inventor Sehat Sutardja

Sehat Sutardja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160358909
    Abstract: Systems and methods are provided for using and manufacturing a semiconductor device. A semiconductor device comprises an array of transistors, wherein each respective transistor in at least some of the transistors in the array of transistors (1) is positioned adjacent to a respective first neighboring transistor and a respective second neighboring transistor in the array of transistors, (2) has a source region that shares a first contact with a source region of the respective first neighboring transistor, and (3) has a drain region that shares a second contact with a drain region of the respective second neighboring transistor.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 8, 2016
    Inventors: Sehat Sutardja, Winston Lee, Peter Lee, Runzi Chang
  • Patent number: 9507543
    Abstract: A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: November 29, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Son Hong Ho
  • Publication number: 20160320981
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventor: Sehat Sutardja
  • Patent number: 9480112
    Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: October 25, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang
  • Patent number: 9477611
    Abstract: A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: October 25, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 9466596
    Abstract: A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: October 11, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Patent number: 9455644
    Abstract: A controller including a switch, a first module, a second module, and a control module. The switch receives current from an inductor and bypasses a portion of the current from being received by a load. The switch is cycled between a first state and a second state at a frequency. The first module, for a first cycle of the switch, determines a first amount of time the switch is in the first state. The second module, based on the first amount of time, determines a second amount of time for a level of the current to decrease to a predetermined level. The second amount of time begins during the first cycle and when the switch transitions from the first state to the second state. The control module, based on the second amount of time and prior to the current decreasing to the predetermined level, changes the frequency of the switch.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 27, 2016
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Jianqing Lin
  • Patent number: 9454991
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: September 27, 2016
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9445475
    Abstract: A light emitting diode (LED) lighting system includes a first string of first LEDs emitting light having a first color. A second string of second LEDs emits light having a second color and connected in series with the first string of first LEDs; A first switch and a second switch are connected in series. A regulator module is configured to modulate the first switch and the second switch to provide a desired current ratio. The desired current ratio corresponds to a ratio of a first current through the first string of first LEDs to a second current through the second string of second LEDs.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 13, 2016
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang
  • Patent number: 9444510
    Abstract: A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 13, 2016
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Poh Boon Leong, Albert Wu, Long-Ching Wang, Sehat Sutardja
  • Publication number: 20160239429
    Abstract: A data access system including a storage device and a processor, which includes one or more levels of cache (LOC). In response to data required by the processor not being within the LOC, the processor generates a physical address to be accessed within the storage device in order to retrieve the data. The storage device includes a main memory and a cache module, which is configured as a final level of cache (FLOC) to be accessed by the processor prior to accessing the main memory. The cache module includes a controller that, in response to the data not being cached within the LOC, converts the physical address into a virtual address within the FLOC. The FLOC uses the virtual address to determine whether the data is within the FLOC. If the data is not within the FLOC, the cache module or the processor retrieves the data from the main memory.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventor: Sehat Sutardja
  • Publication number: 20160240459
    Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Sehat Sutardja, Shiann-Ming Liou, Huahung Kao
  • Patent number: 9408274
    Abstract: A system including a first set of light emitting diodes, a second set of light emitting diodes, and a control module. The first set of light emitting diodes is configured to emit blue light having first wavelengths in a first wavelength range in a spectrum of blue light. The first set of light emitting diodes includes a green phosphor configured to convert the blue light having the first wavelengths to green light. The second set of light emitting diodes is configured to emit blue light having second wavelengths in a second wavelength range in the spectrum of blue light. The second set of light emitting diodes includes a red phosphor configured to convert the blue light having the second wavelengths to red light. The first wavelength range is less than the second wavelength range. The control module is configured to control currents through the first set of light emitting diodes and the second set of light emitting diodes.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: August 2, 2016
    Assignee: Marvell World Trade LTD.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Patent number: 9407562
    Abstract: A network switch including a physical layer device and a media access controller. The physical layer device includes an auto-negotiation circuit configured to negotiate a first data rate for transmission of data between the physical layer device and a network client external to the network switch, and a first serializer interface configured to receive the first data rate from the auto-negotiation circuit. The media access controller includes a second serializer interface. The first serializer interface of the physical layer device is configured to, based on the negotiated first data rate received from the auto-negotiation circuit, selectively replicate portions of data received from the network client, and transmit the data to the second serializer interface of the media access controller at a second data rate regardless of the first data rate negotiated between the auto-negotiation circuit and the network client. The first data rate and the second data rate are different.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 2, 2016
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, William Lo
  • Patent number: 9397036
    Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate having (i) a first side configured to receive a semiconductor die and (ii) a second side disposed opposite to the first side. The substrate comprises a printed circuit board material. The apparatus further comprises an interposer that is (i) disposed in the substrate and (ii) configured to electrically couple the first side of the substrate and the second side of the substrate. The interposer comprises a semiconductor material.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: July 19, 2016
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 9397552
    Abstract: A system including a converter and a snubber circuit. The converter converts an alternating current voltage into a direct current voltage and outputs the direct current voltage across an inductance and a switch connected in series. The inductance has a center tap connected to a node, which is connected to a load. In response to the switch being turned on, a first current flows through the inductance and the switch. In response to the switch being turned off, a second current flows from the node to the load. The snubber circuit is connected across the node and a junction of the inductance and the switch. In response to the switch being turned off, the snubber circuit receives a third current from the junction, and supplies a first portion of the third current to the node. The second current and the first portion of the third current flow through the load.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: July 19, 2016
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9363346
    Abstract: A Voice Over Internet Protocol (VOIP) phone comprises a network interface that communicates with a medium. A control module communicates with the network interface and controls operation of the VOIP phone. A coder/decoder module communicates with the control module. A microphone outputs audio signals to the coder/decoder module. An audio output device receives audio signals from the coder/decoder module. An input/output interface receives user input. The control module and the network interface transmit the user input as packets to a network appliance to adjust an operating parameter of the network appliance.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: June 7, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Hubertus Notohamiprodjo
  • Patent number: 9350360
    Abstract: A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 24, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 9350234
    Abstract: A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: May 24, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Ashutosh Verma, Shafiq M. Jamal, Thomas B. Cho, Sehat Sutardja
  • Patent number: 9337772
    Abstract: An impulse generation circuit for a voltage controlled oscillator includes a zero-crossing detector configured to detect a zero-crossing time of an output signal of the voltage controlled oscillator. The zero-crossing time corresponds to a time that the output signal crosses from a first polarity to a second polarity. A delay circuit is configured to wait for a delay period based on the zero-crossing time and a voltage peak of the output signal. An impulse generation module is configured to generate an impulse subsequent to the delay period. An energy injector is configured to, in response to the impulse, connect a supply voltage to the output signal of the voltage controlled oscillator for a duration of the impulse.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: May 10, 2016
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sehat Sutardja