Abstract: A system including a first set of light emitting diodes, a second set of light emitting diodes, and a control module. The first set of light emitting diodes is configured to emit blue light having first wavelengths in a first wavelength range in a spectrum of blue light. The first set of light emitting diodes includes a green phosphor configured to convert the blue light having the first wavelengths to green light. The second set of light emitting diodes is configured to emit blue light having second wavelengths in a second wavelength range in the spectrum of blue light. The second set of light emitting diodes includes a red phosphor configured to convert the blue light having the second wavelengths to red light. The first wavelength range is less than the second wavelength range. The control module is configured to control currents through the first set of light emitting diodes and the second set of light emitting diodes.

Abstract: A system including a converter and a snubber circuit. The converter converts an alternating current voltage into a direct current voltage and outputs the direct current voltage across an inductance and a switch connected in series. The inductance has a center tap connected to a node, which is connected to a load. In response to the switch being turned on, a first current flows through the inductance and the switch. In response to the switch being turned off, a second current flows from the node to the load. The snubber circuit is connected across the node and a junction of the inductance and the switch. In response to the switch being turned off, the snubber circuit receives a third current from the junction, and supplies a first portion of the third current to the node. The second current and the first portion of the third current flow through the load.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate having (i) a first side configured to receive a semiconductor die and (ii) a second side disposed opposite to the first side. The substrate comprises a printed circuit board material. The apparatus further comprises an interposer that is (i) disposed in the substrate and (ii) configured to electrically couple the first side of the substrate and the second side of the substrate. The interposer comprises a semiconductor material.

Abstract: A Voice Over Internet Protocol (VOIP) phone comprises a network interface that communicates with a medium. A control module communicates with the network interface and controls operation of the VOIP phone. A coder/decoder module communicates with the control module. A microphone outputs audio signals to the coder/decoder module. An audio output device receives audio signals from the coder/decoder module. An input/output interface receives user input. The control module and the network interface transmit the user input as packets to a network appliance to adjust an operating parameter of the network appliance.

Abstract: A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.

Abstract: A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage.

Abstract: An impulse generation circuit for a voltage controlled oscillator includes a zero-crossing detector configured to detect a zero-crossing time of an output signal of the voltage controlled oscillator. The zero-crossing time corresponds to a time that the output signal crosses from a first polarity to a second polarity. A delay circuit is configured to wait for a delay period based on the zero-crossing time and a voltage peak of the output signal. An impulse generation module is configured to generate an impulse subsequent to the delay period. An energy injector is configured to, in response to the impulse, connect a supply voltage to the output signal of the voltage controlled oscillator for a duration of the impulse.

Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Abstract: A data access system including a storage device and a processor, which includes one or more levels of cache (LOC). In response to data required by the processor not being within the LOC, the processor generates a physical address to be accessed within the storage device in order to retrieve the data. The storage device includes a main memory and a cache module, which is configured as a final level of cache (FLOC) to be accessed by the processor prior to accessing the main memory. The cache module includes a controller that, in response to the data not being cached within the LOC, converts the physical address into a virtual address within the FLOC. The FLOC uses the virtual address to determine whether the data is within the FLOC. If the data is not within the FLOC, the cache module or the processor retrieves the data from the main memory.

Abstract: Embodiments of the present disclosure provide a method of making a metal-oxide semiconductor (MOS) device. The method comprises providing an apparatus that comprises a common source and drain well disposed within a substrate, and a gate disposed on the substrate, wherein the gate is substantially encapsulated within layers of the apparatus. The method further comprises removing a portion of the substrate and creating a shallow trench isolation (STI) structure through the substrate such that the STI structure engages the common source and drain well.

Abstract: Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate.

Abstract: Aspects of the disclosure provide a circuit that includes a driver circuit and a current limiter circuit. The driver circuit is configured to drive a load with an output current when the load is coupled with the driver circuit. The current limiter circuit is configured to turn on a path to deplete a portion of the output current from the driver circuit in order to prevent a load current flowing through the load from exceeding a current limit.

Abstract: A data access system including a storage device and a processor, which includes one or more levels of cache (LOC). In response to data required by the processor not being within the LOC, the processor generates a physical address to be accessed within the storage device in order to retrieve the data. The storage device includes a main memory and a cache module, which is configured as a final level of cache (FLOC) to be accessed by the processor prior to accessing the main memory. The cache module includes a controller that, in response to the data not being cached within the LOC, converts the physical address into a virtual address within the FLOC. The FLOC uses the virtual address to determine whether the data is within the FLOC. If the data is not within the FLOC, the cache module or the processor retrieves the data from the main memory.

Abstract: Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.

Abstract: A system including a first core to execute instructions associated with an application at a first speed based on a first instruction set and a second core to execute the instructions associated with the application at a second speed based on a second instruction set. The first speed is greater than the first speed. The second instruction set is a subset of the first instruction set. A first memory stores an operating system. The operating system includes a kernel that provides services to the application. A core switching module loads into a second memory after the operating system is booted, where the second memory is separate from the first memory, switches execution of the instructions associated with the application between the first core and the second core, and switches the execution of the instructions associated with the application between the first core and the second core transparently to the operating system.

Abstract: A differential power amplifier including a push-pull pair of transistors, a capacitance, a first inductance, and a second inductance. The push-pull pair of transistors includes first and second transistors. The first transistor includes control and output terminals. The second transistor includes input and control terminals. The control terminals of the first and second transistors collectively receive a differential input signal. The output and input terminals collectively provide a differential output signal. The capacitance is connected to the output and input terminals. The first capacitance cancels first harmonics at the output terminal of the first transistor with second harmonics at the input terminal of the second transistor. The first transistor and the first inductance are connected in series between a voltage source and a reference terminal. The second transistor and the second inductance are connected in series between the voltage source and the reference terminal.

Abstract: A system including a plurality of switches and a comparator. The plurality of switches is configured to respectively supply a plurality of currents via respective terminals to a plurality of sets of light emitting diodes. The sets of light emitting diodes are configured to respectively output light having wavelengths in a plurality of wavelength ranges in a spectrum of blue light. The comparator is configured to compare a reference voltage to a voltage at one of the terminals of one of the plurality of switches connected to one of the sets of light emitting diodes, and to adjust, based on the comparison, biasing of the plurality of switches to maintain a predetermined ratio of the plurality of currents.

Abstract: An integrated circuit package including a first substrate, a first die, a second die, a second substrate, and a system on chip. The first substrate includes a first portion including first connections, a second portion including no connections, a third portion including second connections, a first opening between the first portion and the second portion, and a second opening between the second portion and the third portion. The first die is arranged on the first substrate. The first die includes third connections to connect to the first connections via the first opening. The second die is arranged adjacent to the first die on the first substrate. The second die includes fourth connections to connect to the second connections via the second opening. The second substrate is connected to the first substrate. The system on chip is arranged on the second substrate between the first substrate and the second substrate.

Abstract: A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.

Abstract: A circuit including: a die a first substrate and at least one active device; an integrated passive device including a first layer, a second substrate, a second layer and an inductance; and a third layer. The inductance includes vias and is an electrostatic discharge inductance. The vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars. The pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.