Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

Abstract: A system includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to amplify an input signal and generate first output signals. The first amplifier stage includes a common-source differential amplifier. The common-source differential amplifier includes a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) having source terminals connected to a common potential. The second amplifier stage includes a first differential amplifier and a second differential amplifier configured to respectively generate first and second differential outputs based on the first output signals. Each of the first and second differential amplifiers includes a plurality of MOSFETs having source terminals connected to the common potential via a respective balun.

Abstract: A transceiver of a first network device including an autonegotiation circuit and a first serializer interface. The auto-negotiation circuit is to negotiate a first data rate for transmission of data between the first network device and a second network device. The first serializer interface to receive the negotiated first data rate from the auto-negotiation circuit, receive first data from the second network device at the negotiated first data rate, replicate portions of the first data received from the second network device in accordance with the negotiated first data rate, and transmit, at a second data rate different from the first data rate, the first data including the replicated portions from the first serializer interface to a second serializer interface of the first network device.

Abstract: A data access system including a storage drive, processor and cache module. The processor, in response to data required by the processor not being cached within one or more levels of cache of the processor, generates a first physical address (PA). The cache module includes a memory and first and second controllers. The memory is a final level of cache. The first controller converts the first PA into a virtual address. The second controller: converts the virtual address into a second PA; based on the second PA, determines whether the data is cached within the memory; and if the data is cached, accesses and forwards the data to the processor. The first or second controller determines whether a cache miss has occurred and, in response to a cache miss and based on the second PA or a third PA of the storage drive, retrieves the data from the storage drive.

Abstract: In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

Abstract: A system includes first, second, and third sets of LEDs. The first set of LEDs generates ultraviolet light and converts the ultraviolet light to blue light using a phosphor coated on the first set of LEDs. The second and third sets of LEDs generate blue light and convert the blue light to green, yellow, and red light using phosphors coated on the second and third sets of LEDs. The second set of LEDs outputs less red light than green light. The third set of LEDs outputs less green light than red light. A combination of the blue, green, yellow, and red light output by the first, second, and third sets of LEDs produces white light.

Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: Systems and methods are provided for using and manufacturing a semiconductor device. A semiconductor device comprises an array of transistors, wherein each respective transistor in at least some of the transistors in the array of transistors (1) is positioned adjacent to a respective first neighboring transistor and a respective second neighboring transistor in the array of transistors, (2) has a source region that shares a first contact with a source region of the respective first neighboring transistor, and (3) has a drain region that shares a second contact with a drain region of the respective second neighboring transistor.

Abstract: A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module.

Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.

Abstract: A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.

Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.

Abstract: A controller including a switch, a first module, a second module, and a control module. The switch receives current from an inductor and bypasses a portion of the current from being received by a load. The switch is cycled between a first state and a second state at a frequency. The first module, for a first cycle of the switch, determines a first amount of time the switch is in the first state. The second module, based on the first amount of time, determines a second amount of time for a level of the current to decrease to a predetermined level. The second amount of time begins during the first cycle and when the switch transitions from the first state to the second state. The control module, based on the second amount of time and prior to the current decreasing to the predetermined level, changes the frequency of the switch.

Abstract: A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.

Abstract: A light emitting diode (LED) lighting system includes a first string of first LEDs emitting light having a first color. A second string of second LEDs emits light having a second color and connected in series with the first string of first LEDs; A first switch and a second switch are connected in series. A regulator module is configured to modulate the first switch and the second switch to provide a desired current ratio. The desired current ratio corresponds to a ratio of a first current through the first string of first LEDs to a second current through the second string of second LEDs.

Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Abstract: A data access system including a storage device and a processor, which includes one or more levels of cache (LOC). In response to data required by the processor not being within the LOC, the processor generates a physical address to be accessed within the storage device in order to retrieve the data. The storage device includes a main memory and a cache module, which is configured as a final level of cache (FLOC) to be accessed by the processor prior to accessing the main memory. The cache module includes a controller that, in response to the data not being cached within the LOC, converts the physical address into a virtual address within the FLOC. The FLOC uses the virtual address to determine whether the data is within the FLOC. If the data is not within the FLOC, the cache module or the processor retrieves the data from the main memory.