Abstract: A method for fabricating a DRAM cell capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate wherein a storage node is formed on a buried contact pad in self-alignment. The method comprises forming a second insulator layer on the first insulator layer including the buried contact pad. An etching stopper layer is next formed on the second insulator layer. Sequentially, a third insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the third insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on both sidewalls of the top via hole.

Abstract: Integrated buffer circuits include an output driver powered at a first power supply voltage (EVC) and a voltage boosting circuit which drives an input (DOK) of the output driver and is powered at a second power supply voltage (VINTQ) having a magnitude less than a magnitude of the first power supply voltage. An internal power supply voltage generator is provided which generates the second power supply voltage at a level which varies inversely with increases in the first power supply voltage in order to minimize timing skew associated with the output driver. This is achieved by lowering the voltage of the signal applied to the input (DOK) of the output driver to compensate for the output driver being powered at an increased first power supply voltage.

Abstract: Integrated power supply voltage generators include a boosted voltage generator which generates a boosted voltage signal (Vpp) at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal (VINTA*), and a circuit which is responsive to a first reference voltage (VREFA) and the boosted voltage signal (Vpp) and generates the internal power supply voltage signal (VINTA*) at a second level which is less than the first level throughout the set-up time interval.

Abstract: A semiconductor memory device having a plurality of memory array banks, a plurality of active array voltage generators, a standby array voltage generator and a plurality of switching means is provided. The semiconductor memory device includes a plurality of memory array banks in which information is stored, a plurality of active array voltage generators connected to the memory array banks, for generating predetermined active voltages in response to memory array bank enable signals for activating the memory array banks, a standby array voltage generator for generating a predetermined standby voltage so that the memory array banks are maintained in a standby state for operation, and a plurality of switching means connected between the memory array banks and the standby array voltage generator, for disconnecting the output of the standby array voltage generator from memory array banks in response to memory array bank enable signals for activating the memory array banks.

Abstract: A column select line control circuit for a synchronous semiconductor memory device increases the time margin for writing input data to memory cells in prefetch mode by delaying the disablement of the column select lines during a write operation, thereby extending the time for writing data to the cells. The control circuit includes a column select line control circuit that generates enable and disable signals in response to an internal clock signal, and a column decoder that enables and disables a column select line in response to the enable and disable signals. In pipeline mode, the column select line control circuit generates the disable signal by delaying the internal clock signal and generates the enable signal by delaying and inverting the internal clock signal. In prefetch mode, the column select line control signal adds an additional delay to both the enable and disable signals, but only during write operations.

Abstract: In a semiconductor memory device, a plurality of output buffers, one for each output data bit, are powered by an internal voltage control circuit so as to provide high speed operation yet minimize power consumption. The internal voltage control circuit inclues multiple internal voltage generators. Responsive to the number of output buffers in use during a read operation, one or more of the voltage generators are activated to power the output buffers. Additionally, the current capacity of each of the individual voltage generators is controlled responsive to the number of output buffers in use during the read operation, so that bandwidth of the memory device is maximized but power is not wasted.

Abstract: Preferred integrated circuit memory devices have the capability of connecting a sense amplifier to multiple arrays of memory one-at-a-time or simultaneously, in response to first and second control signals, respectively. These memory devices include first and second memory arrays which have first and second pairs of differential input/output lines electrically coupled thereto, respectively. A sense amplifier is also provided having first and second pairs of differential input/output lines. To provide independent or simultaneous access to the first and second memory arrays by the sense amplifier, preferred isolation and equalization circuits are provided.

Abstract: Voltage boosting circuits include backup voltage boosting circuits which are enabled during high current loading conditions when voltage sags in the potential of a boosted signal line(s) are encountered, and which provide independent level detection capability to bypass main voltage level detectors when relatively severe voltage sags are anticipated. In particular, voltage boosting circuits are provided which contain a main voltage boosting circuit and a backup voltage boosting circuit therein. The main voltage boosting circuit is typically powered at a first reference potential (e.g., Vcc) and preferably contains a main level detector, a built-in oscillator and a main pump coupled in series to drive a signal line (e.g., Vpp) to a boosted reference potential which is greater than the first reference potential, if a potential of the signal line drops below a second reference potential.

Abstract: A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an input voltage to a desired level. The voltage pumping circuits are driven in response to at least two bank selection control signals. The voltage pumping circuits are arranged in the semiconductor memory device in a proper manner to efficiently perform the voltage pumping operation, so as to increase the pumping efficiency. Further, the proper arrangement of the voltage pumping circuits contributes to the integration of the semiconductor memory device.

Abstract: There is provided in the present invention a signal generator which generates a bit line equalization signal and a signal generator which generates a sense amplifier equalization signal to control the bit line equalization circuit and the sense amplifier equalization circuit, respectively. The generated bit line equalization signal and sense amplifier equalization signal both have a voltage level that is at least about equal to, and preferably greater than, an external power supply voltage. The signals generated by these signal generators can thus be used by operating voltages which are much less than was previously possible.

Abstract: Integrated circuit chips with multiplexed input/output pads include means for expanding the functional and diagnostic capability of the circuit by increasing the effective number of input/output pads connected thereto so that more information can be provided to and from the chip. In particular, multiplexing means preferably provides the capability of accessing any one of a plurality of signal lines in the circuit from each input/output pad. This expanded capability is preferably achieved using one or more selection control signals which can be generated internally or externally to a chip containing the integrated circuit.

Abstract: A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.

Abstract: The voltage boosting circuit of the present invention includes a voltage converting circuit connected between an oscillator and a pair of pumping capacitors. The pair of pumping capacitors are then connected to a single transmission transistor, which outputs a boosted voltage that is derived from the combination of a precharge voltage placed on the source of the transmission transistor and the voltage stored on the pumping capacitors. The presence of the voltage converting circuit, which uses cross-connected PMOS transistors coupled to ground through a pair of NMOS transistors and establishes a differential amplifier, substantially eliminates the body effect problems that would otherwise occur.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a power supply voltage detecting circuit of a semiconductor memory device which senses a voltage level of the power supply voltage. A power supply voltage detecting circuit of the present invention includes a circuit for generating a power supply voltage detecting signal by receiving a power supply voltage and a control circuit for generating a control signal in order to operate the circuit for generating the power supply voltage detecting signal when being in a specific mode state. The power supply voltage detecting circuit according to the present invention can reduce power consumption by cutting off a standby-current, since the power supply voltage detecting circuit is enabled during an activation of a chip.

Abstract: A peripheral/refresh control circuit for a semiconductor memory device, e.g., a dynamic random access memory (DRAM), which includes a first pull-up device connected between a supply voltage and the pull-up node of a sense amplifier, the first pull-up device having a first mode of operation wherein the power supply voltage is coupled to the pull-up node and a second mode of operation wherein the power supply voltage is isolated from the pull-up node, a second pull-up device coupled between a boosting voltage and the pull-up node, the second pull-up device having a first mode of operation wherein the boosting voltage is coupled to the pull-up node and a second mode of operation wherein the boosting voltage is isolated from the pull-up node, a first pull-up control circuit for selectively switching the first pull-up device between its first and second modes of operation, and a second pull-up control circuit for selectively switching the second pull-up device between its first and second modes of operation.

Abstract: A semiconductor memory device includes a refresh timer for generating a refresh clock pulse, a binary counter for generating a predetermined number of signals of different frequencies and a circuit for generating a self-refresh enable signal in response to the signal transmitted from the binary counter. A back-bias clock pulse generator is also included having first, second and third selectors, of which the third selector selects one of the signals transmitted from the binary counter in response to a signal output from each of the first and second selectors. A back-bias generator having an oscillator and a back-bias voltage detecting circuit and a selection circuit for receiving the output signal from the back-bias voltage detection circuit is attached thereto. A signal is transmitted to the oscillator in response to the self-refresh enable signal.