Patents by Inventor Sei-Seung Yoon

Sei-Seung Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080219043
    Abstract: Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations.
    Type: Application
    Filed: June 29, 2007
    Publication date: September 11, 2008
    Applicant: QUALCOMM INCORPORATED
    Inventors: Sei Seung Yoon, Seung H. Kang, Medi Hamidi Sani
  • Publication number: 20080137458
    Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
    Type: Application
    Filed: January 18, 2008
    Publication date: June 12, 2008
    Inventors: Sei Seung Yoon, Charles L. Ingalls, David Pinney, Howard C. Kirsch
  • Publication number: 20080141190
    Abstract: Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.
    Type: Application
    Filed: October 17, 2007
    Publication date: June 12, 2008
    Applicant: QUALCOMM INCORPORATED
    Inventors: Seong-Ook Jung, Sei Seung Yoon, Hyunwoo Nho
  • Publication number: 20080101143
    Abstract: A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing control circuit. The memory array includes M rows and N columns of memory cells and a column of dummy cells. The word line drivers drive word lines for the rows of memory cells. The dummy word line driver drives a dummy word line for at least one dummy cell in the column of dummy cells. The timing control circuit generates enable signals having configurable delay, which may be obtained with an acceleration circuit that provides variable drive for a dummy bit line coupled to the column of memory cells. The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 1, 2008
    Inventors: Seong-Ook Jung, Sei Seung Yoon, Yi Han
  • Patent number: 7345937
    Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: March 18, 2008
    Assignee: Micron Technology, Inc
    Inventors: Sei Seung Yoon, Charles L. Ingalls, David Pinney, Howard C. Kirsch
  • Patent number: 7324394
    Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: January 29, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Sei-Seung Yoon, Jin-Man Han, Seong-Ook Jung
  • Patent number: 7277310
    Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sei Seung Yoon, Charles L. Ingalls, David Pinney, Howard C. Kirsch
  • Patent number: 7254074
    Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sei Seung Yoon, Charles L. Ingalls, David Pinney, Howard C. Kirsch
  • Patent number: 7193914
    Abstract: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: March 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sei Seung Yoon, Charles L. Ingalls, David Pinney, Howard C. Kirsch
  • Patent number: 7006398
    Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: February 28, 2006
    Assignee: T-RAM, Inc.
    Inventors: Sei-Seung Yoon, Jin-Man Han, Seong-Ook Jung
  • Patent number: 6958931
    Abstract: A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: October 25, 2005
    Assignee: T-RAM, Inc.
    Inventors: Sei-Seung Yoon, Seong-Ook Jung
  • Patent number: 6903987
    Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: June 7, 2005
    Assignee: T-Ram, Inc.
    Inventors: Sei-Seung Yoon, Jin-Man Han, Seong-Ook Jung
  • Patent number: 6735113
    Abstract: The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 11, 2004
    Assignee: T-Ram, Inc.
    Inventors: Sei-Seung Yoon, Seong-Ook Jung
  • Publication number: 20040071013
    Abstract: The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Applicant: T-RAM, Inc.
    Inventors: Sei-Seung Yoon, Seong-Ook Jung
  • Patent number: 6721220
    Abstract: A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: April 13, 2004
    Assignee: T-RAM, Inc.
    Inventors: Sei-Seung Yoon, Seong-Ook Jung
  • Publication number: 20040022109
    Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 5, 2004
    Applicant: T-RAM, Inc.
    Inventors: Sei-Seung Yoon, Jin-Man Han, Seong-Ook Jung
  • Publication number: 20040004880
    Abstract: A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.
    Type: Application
    Filed: July 5, 2002
    Publication date: January 8, 2004
    Applicant: T-Ram, Inc.
    Inventors: Sei-Seung Yoon, Seong-Ook Jung
  • Patent number: 6529423
    Abstract: An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: March 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sei-seung Yoon, Sang-pyo Hong
  • Patent number: 6359459
    Abstract: Integrated circuits and methods use a margin test voltage generator that is powered at a first power supply voltage to generate a second power supply voltage that has a magnitude that is less than the magnitude of the first power supply voltage. During a low supply voltage margin test, a first logic circuit is powered at the first power supply voltage while a second logic circuit, which is the subject of the test, is powered at the second power supply voltage. As a result, the first power supply voltage may remain at a sufficient magnitude to reliably power other devices or components that are not undergoing the low supply voltage margin test.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: March 19, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sei-seung Yoon, Sang-pyo Hong
  • Patent number: 6222787
    Abstract: Integrated circuit memory devices include a control circuit that generates an active first control pulse (e.g., PR) having a first duration, in response to an active strobe pulse (e.g., /RAS) that may be generated during a data reading operation. To improve the reliability of the data reading operation and any subsequent data restore operation, particularly when the duration of the active strobe pulse is relatively short, a pulse width extension circuit is provided. The pulse width extension circuit converts the active first control pulse into an active second control pulse (e.g., PAIVCE2) having a second duration greater than the first duration. This active second control pulse is then provided as a control input to an internal voltage generator. The internal voltage generator is provided to drive a first supply signal line (e.g., AIVC2) at a first supply voltage in response to the active second control pulse.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: April 24, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sei-Seung Yoon, Il-Man Bae, Gi-Hong Kim