Patents by Inventor Sei-Seung Yoon

Sei-Seung Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetic element utilizing protective sidewall passivation
    Patent number: 8482966
    Abstract: Exemplary embodiments of the invention are directed to magnetic elements including a passivation layer for isolation from other on-chip elements. One embodiment is directed to an apparatus comprising a magnetic tunnel junction (MTJ) element. The MTJ element comprises: a first ferromagnetic layer; a second ferromagnetic layer; an insulating layer disposed between the first and second ferromagnetic layers; and an MTJ passivation layer forming protective sidewalls disposed adjacent to the first ferromagnetic layer, the second ferromagnetic layer, and the insulating layer.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 9, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Seung H. Kang, Sei Seung Yoon
  • Registers with full scan capability
    Patent number: 8438433
    Abstract: A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: May 7, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Hari M. Rao, Sei Seung Yoon, Nan Chen
  • Code-Based Differential Charging of Bit Lines of a Sense Amplifier
    Publication number: 20130058172
    Abstract: A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Hari M. Rao, Esin Terzioglu, Sei Seung Yoon
  • System and method of operating a memory device
    Patent number: 8279659
    Abstract: A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 2, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Sung Il Cho, Sei Seung Yoon, Naveen Gundubogula, Mohamed H. Abu-Rahma, Dongkyu Park
  • Memory device for resistance-based memory applications
    Patent number: 8228714
    Abstract: In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: July 24, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Anosh B. Davierwalla, Cheng Zhong, Dongkyu Park, Mohamed Hassan Abu-Rahma, Mehdi Hamidi Sani, Sei Seung Yoon
  • Memory read stability using selective precharge
    Patent number: 8223567
    Abstract: A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: July 17, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Mohamed H. Abu Rahma, Ritu Chaba, Nan Chen, Sei Seung Yoon
  • Data integrity preservation in spin transfer torque magnetoresistive random access memory
    Patent number: 8159864
    Abstract: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. A write-back circuit configured to detect a read value of the bit cell and is configured to write back the read value to the bit cell after a read operation.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: April 17, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Seung H. Kang
  • System and method of resistance based memory circuit parameter adjustment
    Patent number: 8161430
    Abstract: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: April 17, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon
  • Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size
    Patent number: 8144509
    Abstract: Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 27, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Mehdi Hamidi Sani, Seung H. Kang, Sei Seung Yoon
  • Registers with Full Scan Capability
    Publication number: 20120072793
    Abstract: A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Hari M. Rao, Sei Seung Yoon, Nan Chen
  • Dual power scheme in memory circuit
    Patent number: 8139426
    Abstract: A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the higher level address signal and, in response, provide word line signals. Write drivers receive low level data input signals and configure bitlines in response to the received input. Memory cells are responsive to the word line signals and to the configured bit lines for storing data therein.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: March 20, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Dongkyu Park, Sei Seung Yoon
  • Data protection scheme during power-up in spin transfer torque magnetoresistive random access memory
    Patent number: 8134856
    Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines and word lines. The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: March 13, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Seung H. Kang
  • Flexible word-line pulsing for STT-MRAM
    Patent number: 8130535
    Abstract: A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM).
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: March 6, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Hari M. Rao, Sei Seung Yoon, Medhi Sani, Seung Duk Lee, Sung Cho
  • System and method to read and write data a magnetic tunnel junction element
    Patent number: 8130534
    Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: March 6, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Mohamed Hassan Abu-Rahma, Seung-Chul Song, Sei Seung Yoon, Dongkyu Park, Cheng Zhong, Anosh B. Davierwalla
  • Word line voltage control in STT-MRAM
    Patent number: 8107280
    Abstract: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: January 31, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Mehdi Hamidi Sani, Seung H. Kang
  • System and method of pulse generation
    Patent number: 8102720
    Abstract: In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: January 24, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Hari Rao, Anosh B. Davierwalla, Dongkyu Park, Sei Seung Yoon
  • Self-timing for a multi-ported memory system
    Patent number: 8082401
    Abstract: Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: December 20, 2011
    Inventors: Hari Rao, Chang Ho Jung, Nan Chen, Sei Seung Yoon
  • Bit line voltage control in spin transfer torque magnetoresistive random access memory
    Patent number: 8027206
    Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 27, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Seung H. Kang
  • Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory
    Patent number: 8004880
    Abstract: Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 23, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Seung H Kang, Medi Hamidi Sani
  • MRAM device with shared source line
    Patent number: 7995378
    Abstract: In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Cheng Zhong, Dongkyu Park, Mohamed H. Abu-Rahma