Abstract: Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.

Abstract: A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit.

Abstract: A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.

Abstract: A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM).

Abstract: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

Abstract: A memory system and method using adaptive word line (WL) pulse widths, including a memory operating according to a wordline (WL) pulse with an associated WL pulse width, and a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test. An adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

Abstract: Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.

Abstract: Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.

Abstract: In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM.

Abstract: A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.

Abstract: Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor.

Abstract: A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing control circuit. The memory array includes M rows and N columns of memory cells and a column of dummy cells. The word line drivers drive word lines for the rows of memory cells. The dummy word line driver drives a dummy word line for at least one dummy cell in the column of dummy cells. The timing control circuit generates enable signals having configurable delay, which may be obtained with an acceleration circuit that provides variable drive for a dummy bit line coupled to the column of memory cells. The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.

Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.

Abstract: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.

Abstract: Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations.

Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit.

Abstract: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. A write-back circuit configured to detect a read value of the bit cell and is configured to write back the read value to the bit cell after a read operation.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines and word lines. The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal.