Abstract: A memory-cell array and peripheral circuit elements are formed together on a semiconductor substrate. A first interlayer insulating film is formed, covering the memory-cell array region and peripheral circuit region of the substrate. A first layer of wires is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film, covering the wires of the first layer. A second layer of wires is formed on the second interlayer insulating film. A third interlayer insulating film is formed on the second interlayer insulating film, covering the wires of the second layer. The third interlayer insulating film is processed to have a flat upper surface. A third layer of wires is formed on only that part of the third interlayer insulating film, which lies above the peripheral circuit region. Thereafter, a passivation film is deposited on the third interlayer insulating film.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24).

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first sidewall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: This invention discloses a memory cell threshold voltage shift method effective for the erase or write sequence of a nonvolatile semiconductor memory. First, the threshold voltages VTH of a plurality of memory cells are shifted at once to a range whose upper limit is set to an erase verify voltage VEV. After this, the lower limit of the threshold voltages VTH shifted at once to the range is shifted to a first overerase verify voltage VOEV1 close to the erase verify voltage VEV. Then, the lower limit of the threshold voltages VTH shifted to the first overerase verify voltage VOEV1 to a second overerase verify voltage VOEV2 closer to the erase verify voltage VEV.

Abstract: A method of manufacturing the semiconductor memory comprises element described below; (a) forming a first oxide film on a semiconductor substrate; (b) forming a polysilicon electrode on the first oxide film by sub-steps of forming a low impurity density polysilicon layer, forming a high impurity density polysilicon layer, and forming a low impurity density polysilicon layer in this order; (c) forming a second oxide film on the polysilicon electrode.

Abstract: In a nonvolatile semiconductor memory device using a stacked gate structure type transistor as a memory cell, an N-type well is formed on the surface of a P-type silicon substrate, and a plurality of P-type wells are formed on the surface of the N-type well. The P-type wells are electrically isolated by trenches. A plurality of memory cells are formed on each of the P-type wells, and a P-type contact layer, which is connected to a bias circuit, is formed thereon. When information is read, a reverse bias voltage is selectively applied by the bias circuit between the P-type silicon substrate and the P-type well not including an N-type source diffusion layer of a selected memory cell.

Abstract: A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines.

Abstract: A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passivation film), covering the silicon substrate and serving as an uppermost layer, is formed on an upper portion of the silicon substrate. Thereafter, annealing is performed to discharge water in the BPSG film to an outer portion of an LSI. The annealing is performed under a condition satisfying the following equation of t≧7.86×10−11×L2×exp (9115/T) where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature). Thereby, an amount of electronic trap in a gate oxide film of the transistor can be reduced.

Abstract: A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines.

Abstract: An n-type diffused layer is formed in a p-type semiconductor substrate. A control gate electrode of a memory cell MC is connected with a metal interconnect of a first layer and the metal interconnect is connected with the diffused layer. Moreover, a metal interconnect of the first layer is connected with a metal interconnect of a second layer. An interconnect of the second layer is connected with the output node of a row decoder.

Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first conductive layer. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.

Abstract: A method of manufacturing the semiconductor memory comprises a plurality of steps. The steps include forming a first oxide film on a semiconductor substrate, forming a polysilicon electrode on the first oxide film by the sub-steps of forming a low impurity density polysilicon layer, forming a high impurity density polysilicon layer, and forming a low impurity density polysilicon layer in this order, and forming a second oxide film on the polysilicon electrode.

Abstract: According to this invention, a metal interconnection for the common source diffusion layer of memory cell transistors can be easily formed. An insulating interlayer which covers memory cell transistors is formed on a substrate. A contact hole connected to each drain diffusion layer and a slit-like opening for forming the metal interconnection for the common source diffusion layer are formed on the insulating interlayer. Each contact hole and the slit-like opening are embedded with a refractory metal. The refractory metal in each contact hole is connected to a bit line on the insulating interlayer. In order to connect the refractory metal film in the slit-like opening to only an upper source line, the refractory metal in the slit-like opening crosses under the bit line so as to have an intermediate level of the insulating interlayer in the direction of thickness except for a contact portion with the source line.

Abstract: In a method of manufacturing a semiconductor memory device, before an exposed portion of the element separating isolation film is subjected to etching according to the SAS technique, an isolation film is laminated on the entirety of laminated gate structure, and thereafter, the exposed portion of the element separating isolation film is removed by etching while protecting the side surface of the floating gate with the isolation film.

Abstract: Each of the cell transistors which constitute an EEPROM is set one of the first to fourth threshold voltages, to store one of four different data items. The first and fourth threshold voltages are the lowest and the highest of the four, respectively, and the second threshold voltage is lower than the third threshold voltage. Each cell transistor is set at a neutral threshold voltage when the charge-accumulating layer accumulates no charge. The neutral threshold voltage is higher than the second threshold voltage and lower than the third threshold voltage. The difference between the neutral threshold voltage and one of the four threshold voltages is so small that the self-field of the cell transistor has a low intensity.

Abstract: An SiO.sub.2 film and a PSG film are stacked on a semiconductor substrate. A contact hole is formed through the both films. An Si.sub.3 N.sub.4 film is formed on a side wall of the contact hole as a free ion Na.sup.+ blocking film. An aluminum wiring layer is formed in the contact hole. This arrangement prevents free ions Na.sup.+ from externally migrating through the SiO.sub.2 film and reaching a nonvolatile semiconductor memory cell during and after the formation of the contact hole.

Abstract: Disclosed is a semiconductor memory device which has memory cell transistors each comprising a liner source diffusion layer, a land-shaped drain diffusion layer, a gate oxide film containing a floating gate formed on the channel region between those diffusion layers, and a control gate formed on the gate oxide film. Trenches are formed in the substrate in no contact with the channel regions to isolate the cell transistors from each other.