Patents by Inventor Seiichi Mori

Seiichi Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4990463
    Abstract: In the invention, the thin natural oxide film formed on a surface of a first polycrystalline silicon layer containing an impurity diffused at a high concentration is transformed into a silicon nitride film by rapid nitriding. When the resultant structure is placed in a low-pressure CVD furnace to deposit a silicon nitride film, no natural oxide film is grown on the polycrystalline silicon layer. Hence, when the invention is applied to manufacture of a capacitor for a memory cell, the inter-layer insulative film of the capacitor is not too thick. As a result, a reliable capacitor suitable for micropatterning of elements can be formed between the first and second polycrystalline silicon layers.
    Type: Grant
    Filed: June 29, 1989
    Date of Patent: February 5, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 4952974
    Abstract: An image recording apparatus employs an electrophotographic process wherein a recording medium is fed along a predetermined feed path, a photoconductive drum on which a toner image is formed is arranged below the feed path and a transfer unit is arranged above the feed path oppositley to the photoconductive drum so as to transfer the toner image formed on the photoconductive drum onto the undersurface of the recording medium. An upper component arranged above the photoconductive drum is arranged openably with respect to a lower component in which the photoconductive drum and a unit which is exchangeable are disposed. A detecting member, which detects the presence of the exchangeable unit when the upper component is closed with respect to the lower component, is provided on the upper component.
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: August 28, 1990
    Assignee: Asahi Kogaku Kogyo Kabushiki Kaisha
    Inventor: Seiichi Mori
  • Patent number: 4943836
    Abstract: An ultraviolet erasable nonvolatile seimconductor device has a floating gate, a conrol gate, and a gate insulating layer interlayered between the floating gate and the control gate. The interlayered gate insulating layer consists of three layers, a first silicon oxide layer, a silicon nitride layer layered on the first silicon oxide layer, and a second silicon oxide layer. The second silicon oxide layer as the top layer of the three-layered gate insulating layer is 30 .ANG. or less in thickness.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: July 24, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 4935378
    Abstract: According to a semiconductor device manufacturing method of the invention, a first polycrystalline silicon layer doped with an impurity, a thin oxide film, a second polycrystalline silicon layer, and a silicon nitride film are sequentially formed, one upon the other. The silicon nitride film, the second polycrystalline silicon layer, the thin oxide film, and the first polycrystalline silicon layer are then etched, in a self-aligned manner, by means of a photolithography process. A thick oxide film is formed on a side wall portion of the first polycrystalline silicon layer, using the silicon nitride film as a mask, and after the silicon nitride film is removed, a conductive film is formed on the entire surface. Since a film formation process advances without patterning the first polycrystalline silicon layer, the first polycrystalline silicon layer is not damaged by an RIE process and the like. A defect density of the oxide film formed on the first polycrystalline silicon layer can be reduced.
    Type: Grant
    Filed: March 18, 1988
    Date of Patent: June 19, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 4929982
    Abstract: An electrophotographic printer of the transfer type with separate input bins for holding cut sheet print material and fan-fold form print material. Separate paper paths are provided from each bin to a first function. An input paper path is provided for moving either cut sheet or fan-fold forms from the first function to the transfer station. An output paper path is provided for moving either cut sheet or fan-fold forms from the transfer station through the fuser to a second function. Separate paper paths are provided from the second fuction to stack cut sheet material and fan-fold forms in separate output bins.
    Type: Grant
    Filed: May 18, 1989
    Date of Patent: May 29, 1990
    Assignee: International Business Machines Corporation
    Inventors: Masayuki Ainoya, Takeyuki Ishihara, Tesuo Kanno, Takahiro Kikuchi, Seiichi Mori, Shogo Nobumori, Junji Shirakawa
  • Patent number: 4847667
    Abstract: In a step of forming an interlayer insulation film between memory elements in an ultraviolet erasable nonvolatile semiconductor memory device and an upper metal wiring layer, a thermal oxide film is formed on a semiconductor substrate and around the stacked gate, and a boron and phosphorus doped oxide film is formed on a phosphorus doped oxide film which is formed on the thermal oxide film. Then, a heat treatment is effected to cause the boron and phosphorus doped oxide film to melt and fill the concave portion on the surface of the phosphorus doped oxide film.
    Type: Grant
    Filed: February 24, 1988
    Date of Patent: July 11, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 4616402
    Abstract: A method of manufacturing a semiconductor device with a stacked-gate-electrode structure which includes; forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relationship, forming a floating gate such that it overlies the channel region between the source and drain regions with a gate insulating film therebetween, and forming a control gate such that it overlies the floating gate with an insulating film therebetween. An oxidation-resistant film pattern having a predetermined opening is formed over a non-monocrystalline silicon layer. The non-monocrystalline silicon layer within the opening is selectively oxidized with the oxidation-resistant film pattern as a mask to form a separation insulating film. In this way, a floating gate layer is formed with the portion of the non-monocrystalline silicon layer insulatingly separated.
    Type: Grant
    Filed: May 2, 1985
    Date of Patent: October 14, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 4262041
    Abstract: A process for preparing a composite amphoteric ion exchange membrane, which comprises forming a thin membrane not exceeding 5 microns thick by applying to a surface of a microporous polymer substrate having a physical, selective permeability of its own, a coating consisting of a polymer having either a cation or anion exchange group and a functional group capable of receiving another ion exchange group having an opposite sign from the cation or anion exchange group or a mixture of two polymers one of which has either a cation or an anion exchange group and the other of which has a functional group capable of receiving an ion exchange group having an opposite sign from the cation or anion exchange group, and introducing the ion exchange group having an opposite sign to said functional group to provide a ratio of anion to cation exchange capacity in the range of from 0.5 to 2.0.
    Type: Grant
    Filed: February 2, 1978
    Date of Patent: April 14, 1981
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki Kaisha
    Inventors: Tamiyuki Eguchi, Seiichi Mori, Masaaki Shimokawa