Patents by Inventor Seiichi Nakatani
Seiichi Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10030156Abstract: Disclosed herein is a conductive paste for forming a conductive film, including: (A) a conductive powder; (B) as a first additive, at least one selected from a first group consisting of Se, Te, a compound containing Se, and a compound containing Te; (C) as a second additive, a compound containing at least one element selected from a second group consisting of V, Nb, Ta, Sb, Bi, Mn, Ge, Si, and W; (D) glass frit; (E) an organic binder; and (F) a solvent.Type: GrantFiled: December 5, 2014Date of Patent: July 24, 2018Assignee: KYOTO ELEX CO., LTD.Inventors: Kazuya Takagi, Seiichi Nakatani, Kenichi Harigae, Nobuo Ochiai, Masashi Nakayama, Kairi Otani, Nozomu Hayashida
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Patent number: 9825209Abstract: A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.Type: GrantFiled: December 20, 2013Date of Patent: November 21, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuma Mima, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
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Patent number: 9627583Abstract: There is provided a light-emitting device comprising a light-emitting element. The light-emitting device of the present invention comprises an electrode part for the light-emitting element; a reflective layer provided on the electrode part; and the light-emitting element provided on the reflective layer such that the light-emitting element is in contact with at least a part of the reflective layer, wherein the light-emitting element and the electrode part are in an electrical connection with each other by mutual surface contact via the at least a part of the reflective layer, wherein the electrode part serves as a supporting layer for supporting the light-emitting element, and wherein the electrode part extends toward the outside of the light-emitting element and beyond the light-emitting element.Type: GrantFiled: January 28, 2013Date of Patent: April 18, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Susumu Sawada, Seiichi Nakatani, Koji Kawakita, Yoshihisa Yamashita
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Patent number: 9595651Abstract: A method for manufacturing an electronic component package comprises: (i) preparing a metal foil having opposed principal surface “A” for placement of an electronic component and principal surface “B”, and a through-hole located in an electronic component-placement region of surface “A”; (ii) placing the electronic component on the metal foil such that the electronic component is positioned in the electronic component-placement region, and an opening of the through-hole is capped with an electrode of the electronic component; (iii) forming a sealing resin layer on surface “A” such that the electronic component is covered with the sealing resin layer; and (iv) forming a metal plating layer on surface “B”. A dry plating process and a wet plating process are performed to form the metal plating layer in step (iv) such that the through-hole is filled with the metal plating layer, and the metal foil and the metal plating layer are integrated.Type: GrantFiled: December 20, 2013Date of Patent: March 14, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yoshihisa Yamashita, Seiichi Nakatani, Koji Kawakita, Susumu Sawada
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Patent number: 9541518Abstract: An electrochemical detector is an electrochemical detector for detecting a substance in a liquid by generating a redox cycle, the electrochemical detector comprising: a first working electrode having a first electrode surface, a second working electrode having a second electrode surface, and a plurality of insulating spacer particles, wherein the first and second electrode surfaces are placed so as to face each other so that an electric field is formed between the first and second electrode surfaces, and the plurality of spacer particles are placed along the first and second electrode surfaces so as to separate the first and second electrode surfaces from each other.Type: GrantFiled: December 12, 2012Date of Patent: January 10, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshihisa Yamashita, Seiichi Nakatani, Tetsuyoshi Ogura, Koichi Hirano, Makoto Takahashi, Satoshi Arimoto
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Patent number: 9449944Abstract: There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.Type: GrantFiled: December 20, 2013Date of Patent: September 20, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita
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Patent number: 9449937Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.Type: GrantFiled: August 2, 2013Date of Patent: September 20, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Koji Kawakita, Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita
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Patent number: 9425122Abstract: A method for manufacturing an electronic component packages is provided, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. A combination of a formation process of a plurality of metal plating layers and a patterning process of the plurality of metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, and the patterning process being performed by a patterning of at least two of the plurality of metal plating layers.Type: GrantFiled: December 20, 2013Date of Patent: August 23, 2016Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Koji Kawakita, Seiichi Nakatani, Susumu Sawada, Yoshihisa Yamashita
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Patent number: 9426899Abstract: An electronic component assembly including a first electronic component including a plurality of first electrodes provided on a first major surface of the first electronic component; and a second electronic component including a plurality of second electrodes provided on a first major surface of the second electronic component. A resin including solder powder is provided between the first electronic component and the second electronic component. Also, solder connections are provided to electrically interconnect the first and second electrodes. Elongated grooves are provided in surfaces of the electronic components. The grooves are provided for generation of bubbles during the process for producing the electronic component assembly to promote movement of the solder powder.Type: GrantFiled: April 24, 2008Date of Patent: August 23, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takashi Kitae, Seiichi Nakatani, Seiji Karashima
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Patent number: 9368469Abstract: There is provided a method for manufacturing an electronic component package. The method includes the steps: (i) disposing a metal pattern layer on an adhesive carrier; (ii) placing at least one kind of electronic component on the adhesive carrier, the placed electronic component being not overlapped with respect to the metal pattern layer; (iii) forming a sealing resin layer on the adhesive carrier, and thereby producing a precursor of the electronic component package; (iv) peeling off the adhesive carrier of the precursor, whereby the metal pattern layer and an electrode of the electronic component are exposed at the surface of the sealing resin layer; and (v) forming a metal plating layer such that the metal plating layer is in contact with the exposed surface of the metal pattern layer and the exposed surface of the electrode of the electronic component.Type: GrantFiled: August 2, 2013Date of Patent: June 14, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
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Patent number: 9330811Abstract: There is provided a transparent electrode comprising a supporting substrate, a first transparent electrically-conductive film provided on the supporting substrate, a transparent insulating film provided on the first transparent electrically-conductive film, and a second transparent electrically-conductive film provided on the transparent insulating film. In the transparent electrode of the present invention, all of the first transparent electrically-conductive film, the second transparent electrically-conductive film and the transparent insulating film provided therebetween comprise a metal compound, and the first transparent electrically-conductive film and the second transparent electrically-conductive film have a crystalline structure, whereas the transparent insulating film has an amorphous structure.Type: GrantFiled: May 17, 2013Date of Patent: May 3, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takashi Ichiryu, Yoshihisa Yamashita, Seiichi Nakatani
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Patent number: 9320155Abstract: A ceramic substrate composite includes a conductor pattern composite and an insulating layer on a ceramic substrate. The ceramic substrate composite is formed such that the conductor pattern composite and the insulating layer are provided on the ceramic substrate with each other so that the insulating layer overlaps a part of the conductor pattern composite. The conductor pattern composite is composed of a conductor portion and an insulating portion that exists locally in the conductor portion, and the insulating portion is an insulating material that constitutes the insulating layer.Type: GrantFiled: December 21, 2012Date of Patent: April 19, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Taiji Kuroiwa, Seiichi Nakatani, Yoshihisa Yamashita, Susumu Sawada
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Patent number: 9236338Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.Type: GrantFiled: October 29, 2012Date of Patent: January 12, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Seiichi Nakatani, Koji Kawakita, Susumu Sawada, Yoshihisa Yamashita
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Publication number: 20150280093Abstract: There is provided a light-emitting device comprising a light-emitting element, an element electrode, an extending-wiring electrode and a support. In the light-emitting device of the present invention, the light-emitting element is supported and secured by the support in such a form that a principal surface of the support and an active surface of the light-emitting element are approximately flush with each other. Further, the extending-wiring electrode is in a surface contact with the element electrode such that the extending-wiring electrode extends beyond a periphery of the light-emitting element to the principal surface of the support, wholly covering the active surface of the light-emitting element.Type: ApplicationFiled: August 2, 2013Publication date: October 1, 2015Inventors: Yoshihiro Tomita, Susumu Sawada, Seiichi Nakatani, Koji Kawakita, Yoshihisa Yamashita
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Publication number: 20150236233Abstract: A method for manufacturing an electronic component package comprises: (i) preparing a metal foil having opposed principal surface “A” for placement of an electronic component and principal surface “B”, and a through-hole located in an electronic component-placement region of the principal surface “A”; (ii) placing the electronic component on the metal foil such that the electronic component is positioned in the electronic component-placement region, and an opening of the through-hole is capped with an electrode of the electronic component; (iii) forming a sealing resin layer on the principal surface “A” such that the electronic component is covered with the sealing resin layer; and (iv) forming a metal plating layer on the principal surface “B”. A dry plating process and a subsequent wet plating process are performed to form the metal plating layer in the (iv) such that the through-hole is filled with the metal plating layer, and the metal foil and the metal plating layer are integrated with each other.Type: ApplicationFiled: December 20, 2013Publication date: August 20, 2015Inventors: Yoshihisa Yamashita, Seiichi Nakatani, Koji Kawakita, Susumu Sawada
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Publication number: 20150228619Abstract: There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.Type: ApplicationFiled: December 20, 2013Publication date: August 13, 2015Inventors: Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita
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Patent number: 9107306Abstract: A hybrid substrate includes a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least has a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other.Type: GrantFiled: October 5, 2011Date of Patent: August 11, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Seiichi Nakatani, Koji Kawakita
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Publication number: 20150221842Abstract: There is provided a method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer, wherein in the step (iv), the second metal plating layer is formed to fill a clearance between the first metal plating layer and the metal foil with the second metal plating layer, and thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.Type: ApplicationFiled: December 20, 2013Publication date: August 6, 2015Applicant: Panasonic Intellectual Property Management Co., LtInventors: Kazuma Mima, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
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Publication number: 20150214129Abstract: There is provided a method for manufacturing an electronic component package, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. In the manufacturing method of the present invention, a combination of a formation process of a plurality of metal plating layers and a patterning process of the metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, the patterning process being performed by a patterning of at least two of the metal plating layers.Type: ApplicationFiled: December 20, 2013Publication date: July 30, 2015Inventors: Koji Kawakita, Seiichi Nakatani, Susumu Sawada, Yoshihisa Yamashita
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Publication number: 20150206819Abstract: There is provided a method for manufacturing an electronic component package. The method comprises the steps: (i) forming a package precursor in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer; (ii) disposing a metal foil having a through-hole on the surface of the sealing resin layer such that the through-hole of the metal foil is positioned in an opposed relation to the electrode of the electronic component; and (iii) forming a metal plating layer on the metal foil, wherein the formation of the metal plating layer in the step (iii) is performed by a dry plating process and a subsequent wet plating process, whereby the through-hole is filled with the metal plating layer, and the metal foil and the metal plating layer are integrated with each other.Type: ApplicationFiled: December 20, 2013Publication date: July 23, 2015Inventors: Takashi Ichiryu, Seiichi Nakatani, Yoshihisa Yamashita