Patents by Inventor Seiichi Nakatani

Seiichi Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110049598
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Application
    Filed: November 4, 2010
    Publication date: March 3, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Koichi HIRANO, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20110049218
    Abstract: A liquid resin in which conductive particles are dispersed is supplied to between a circuit substrate and a semiconductor chip disposed so as to face each other and an ultrasonic wave having an amplitude in a perpendicular direction to a surface of the circuit substrate to generate a standing wave in a resin. Then, the conductive particles dispersed in the resin are captured at nodes of the standing wave to form connection bodies of aggregation of the conductive particles between connection terminals of the semiconductor chip and terminals of the circuit substrate. Thus, the semiconductor chip is mounted on the circuit substrate via the connection bodies. The terminals are arrayed so as to be spaced apart from one another by half a wavelength of the standing wave and each of the nodes of the standing wave are generated at a position between the terminals in the resin.
    Type: Application
    Filed: November 5, 2010
    Publication date: March 3, 2011
    Applicant: Panasonic Corporation
    Inventors: Tsukasa SHIRAISHI, Seiichi Nakatani
  • Publication number: 20110042677
    Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprises a metal layer comprising a gate electrode, a source electrode and a drain electrode; a metal oxide film made from a metal which constitutes the metal layer and formed over a surface region of the metal layer; and a semiconductor layer formed above the gate electrode via the metal oxide film. In the flexible semiconductor device, uncovered portions, each of which is not covered with the metal oxide film, are locally formed in the surface region of the metal layer; and also electrical connections are formed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer via the uncovered portions.
    Type: Application
    Filed: November 13, 2009
    Publication date: February 24, 2011
    Inventors: Takeshi Suzuki, Kenichi Hotehama, Koichi Hirano, Seiichi Nakatani
  • Patent number: 7888789
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Patent number: 7875496
    Abstract: A flip chip mounting method includes holding a circuit board (213) and a semiconductor chip (206), aligning the circuit board (213) with the semiconductor chip (206) while holding them with a predetermined gap therebetween, heating the circuit board (213) or the semiconductor chip (206) to a temperature at which solder powder in a solder resin composition (216) formed of solder powder (214) and a resin (215) is melted, supplying the solder resin composition (216) by a capillary phenomenon, and curing the resin (215), wherein the melted solder powder (214) in the solder resin composition (216) is moved through the predetermined gap across which the circuit board (213) and the semiconductor chip (206) are held, and self-assembled and grown, whereby the connection terminals (211) and the electrode terminals (207) are connected to each other electrically.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7859855
    Abstract: A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Tsutomu Mitani
  • Patent number: 7850803
    Abstract: A liquid resin in which conductive particles are dispersed is supplied to between a circuit substrate and a semiconductor chip disposed so as to face each other and an ultrasonic wave having an amplitude in a perpendicular direction to a surface of the circuit substrate to generate a standing wave in a resin. Then, the conductive particles dispersed in the resin are captured at nodes of the standing wave to form connection bodies of aggregation of the conductive particles between connection terminals of the semiconductor chip and terminals of the circuit substrate. Thus, the semiconductor chip is mounted on the circuit substrate via the connection bodies. The terminals are arrayed so as to be spaced apart from one another by half a wavelength of the standing wave and each of the nodes of the standing wave are generated at a position between the terminals in the resin.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsukasa Shiraishi, Seiichi Nakatani
  • Patent number: 7851281
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20100283054
    Abstract: There is provided a method for manufacturing a flexible semiconductor device characterized by comprising (i) a step of forming an insulating film on the upper surface of metal foil, (ii) a step of forming an extraction electrode pattern on the upper surface of the metal foil, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the extraction electrode pattern, (iv) a step of forming a sealing resin layer on the upper surface of the metal foil in such a manner that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) a step of forming electrodes by etching the metal foil, wherein the metal foil is used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v).
    Type: Application
    Filed: July 30, 2009
    Publication date: November 11, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa, Takashi Ichiryu, Takeshi Suzuki
  • Publication number: 20100276691
    Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 4, 2010
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano, Yoshihisa Yamashita, Shingo Komatsu
  • Patent number: 7820021
    Abstract: A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Takashi Kitae, Seiichi Nakatani
  • Publication number: 20100261321
    Abstract: There is provided a method for manufacturing a flexible semiconductor device. The manufacturing method is characterized by comprising (i) a step of forming an insulating film on the upper surface of a resin film, (ii) a step of forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) a step of forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one forming step among the above (i) to (iv) is carried out by a printing method. In the manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.
    Type: Application
    Filed: July 30, 2009
    Publication date: October 14, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa
  • Patent number: 7799607
    Abstract: A process for forming bumps wherein a plurality of fine bumps are uniformly formed with high productivity. In this process, a resin (13) including solder powder and a convection additive (12) is supplied onto a substrate (10) having a plurality of electrodes (11) thereon. And subsequently the substrate (10) is heated to a temperature that enables the solder powder to melt while keeping a flat plate (14) in contact with a surface of the supplied resin (13). During this heating step, the molten solder powder is allowed to self-assemble onto the electrodes (11) so that a plurality of solder balls, resulting from the grown molten solder powder, are concurrently formed on the electrodes (11) in self-alignment manner. Finally, the flat plate (14) is moved away from the surface of the supplied resin (13), and then the resin (13) is removed to provide a substrate (10) having bumps (16) formed on the plurality of the electrodes.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Publication number: 20100224986
    Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 9, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
  • Publication number: 20100203675
    Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217).
    Type: Application
    Filed: April 21, 2010
    Publication date: August 12, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Seiichi NAKATANI, Takashi KITAE, Yoshihisa YAMASHITA, Takashi ICHIRYU, Seiji KARASHIMA
  • Patent number: 7773386
    Abstract: A flexible substrate includes: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Yamashita, Toshio Fujii, Seiichi Nakatani, Takashi Ichiryu, Satoru Tomekawa, Hiroki Yabe
  • Publication number: 20100181558
    Abstract: A semiconductor device having semiconductor elements disposed with higher density and a method for manufacturing the same are provided. An image display device employing the semiconductor device is also provided. A semiconductor device comprises a resin film having a through hole; and a semiconductor element comprising a gate electrode disposed on the inner wall of the through hole, an insulating layer that covers the gate electrode within the through hole, an organic semiconductor disposed on the insulating layer within the through hole, and a source electrode and a drain electrode which are electrically connected to the organic semiconductor.
    Type: Application
    Filed: July 1, 2008
    Publication date: July 22, 2010
    Inventors: Yoshihisa Yamashita, Seiichi Nakatani
  • Publication number: 20100182144
    Abstract: Provided is a RFID magnetic sheet to be attached to an IC tag. The RFID magnetic sheet is provided with a plurality of stripe arranged layers (11a, 11b) whereupon a plurality of magnetic stripes (12) composed of a metal magnetic material are arranged at intervals, and a resin film (10) interposed between the respective stripe arranged layers. The arrangement relationship between the stripe arranged layers is set so that the magnetic stripes on each of the stripe arranged layers intersect with the magnetic stripes on the other stripe arranged layer in a planar shape.
    Type: Application
    Filed: August 6, 2007
    Publication date: July 22, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yoshihisa Yamashita, Seiichi Nakatani, Takashi Ichiryu, Fumio Fukushima, Kuniaki Kiyosue
  • Patent number: 7759162
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7748110
    Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Asahi, Seiji Karashima, Takashi Ichiryu, Seiichi Nakatani, Tousaku Nishiyama, Koichi Hirano, Osamu Shibata, Takeshi Nakayama, Yoshiyuki Saito