Patents by Inventor Seiichi Nakatani

Seiichi Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8525172
    Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa, Takashi Ichiryu, Takeshi Suzuki
  • Publication number: 20130200516
    Abstract: A hybrid substrate according to the present invention comprises a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least comprises a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other.
    Type: Application
    Filed: October 5, 2011
    Publication date: August 8, 2013
    Inventors: Seiichi Nakatani, Koji Kawakita
  • Patent number: 8501583
    Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: August 6, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Kitae, Seiji Karashima, Susumu Sawada, Seiichi Nakatani
  • Patent number: 8435842
    Abstract: A method for manufacturing a flexible semiconductor device comprises (i) forming an insulating film on the upper surface of a resin film, (ii) forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one of the stepsof the above steps (i) to (iv) is carried out by a printing method. With this manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa
  • Patent number: 8367488
    Abstract: A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano
  • Patent number: 8343822
    Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Tatsuo Ogawa, Takashi Ichiryu, Takeshi Suzuki
  • Publication number: 20120319159
    Abstract: There is provided a substrate for light-emitting element, including a mounting surface on which a light-emitting element is to be mounted, the mounting surface being one of two opposed main surfaces of the substrate. The substrate of the present invention is provided with a protection element for the light-emitting element, the protection element comprising a voltage-dependent resistive layer embedded in a body of the substrate, and comprising a first electrode and a second electrode each of which is in connection with the voltage-dependent resistive layer wherein the light-emitting element is to be mounted such that it is positioned in an overlapping relation with the voltage-dependent resistive layer.
    Type: Application
    Filed: February 23, 2011
    Publication date: December 20, 2012
    Inventors: Seiichi Nakatani, Tatsuo Ogawa, Kazuo Kimura, Shigetoshi Segawa
  • Patent number: 8324623
    Abstract: A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: December 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Tetsuyoshi Ogura, Seiichi Nakatani
  • Publication number: 20120286264
    Abstract: There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (a) preparing a metal foil having a concave portion; (b) forming a gate insulating film on a bottom face of the concave portion of the metal foil; (c) forming a semiconductor layer above the bottom face of the concave portion via the gate insulating film while making use of the concave portion as a bank member; and (d) forming a source electrode and a drain electrode such that they make contact with the semiconductor layer.
    Type: Application
    Filed: April 22, 2011
    Publication date: November 15, 2012
    Inventors: Takeshi Suzuki, Seiichi Nakatani, Koichi Hirano
  • Patent number: 8297488
    Abstract: A method for forming bumps 19 on electrodes 32 of a wiring board 31 includes the steps of: (a) supplying a fluid 14 containing conductive particles 16 and a gas bubble generating agent onto a first region 17 including the electrodes 32 on the wiring board 31; (b) disposing a substrate 40 having a wall surface 45 formed near the electrodes 32 for forming a meniscus 55 of the fluid 14, so that the substrate 40 faces the wiring board 31; and (c) heating the fluid 14 to generate gas bubbles 30 from the gas bubble generating agent contained in the fluid 14.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yasushi Taniguchi, Seiichi Nakatani, Kenichi Hotehama, Takashi Kitae, Susumu Sawada
  • Patent number: 8288778
    Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, an organic semiconductor disposed inside the through hole, an insulating film on one end of the organic semiconductor, a gate electrode on the insulating film, a source electrode connected electrically to the other end of the organic semiconductor and a drain electrode connected electrically to the other end of the organic semiconductor.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: October 16, 2012
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
  • Patent number: 8283246
    Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7).
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventors: Takashi Kitae, Seiichi Nakatani, Seiji Karashima, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20120181543
    Abstract: Disclosed are a flexible semiconductor device and manufacturing method therefor whereby the capacitances of capacitor parts of semiconductor elements and the like can be increased while decreasing parasitic capacitances that arise between multilevel interconnections. The disclosed flexible semiconductor device is provided with an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element comprises: a semiconductor layer formed on the top surface of the insulating film; a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer; and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer.
    Type: Application
    Filed: April 14, 2011
    Publication date: July 19, 2012
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano
  • Patent number: 8193526
    Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, a source electrode disposed along the inner wall of the through hole, a drain electrode disposed along the inner wall of the through hole, a gate electrode disposed on the other surface of the resin film opposing the through hole, an insulating layer disposed on the gate electrode at the bottom of the through hole and an organic semiconductor disposed in the through hole so as to contact the source electrode and the drain electrode, wherein the organic semiconductor makes contact with at least a part of the insulating layer at the bottom of the through hole so that a channel is formed in the organic semiconductor in the vicinity of the insulating layer that is in contact therewith.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: June 5, 2012
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
  • Publication number: 20120113500
    Abstract: Provided is an electronic paper that permits a high-quality, large area to be easily created. Also provided is a method for producing the electronic paper. The electronic paper comprises: a first substrate upon which first electrodes are formed and a second substrate upon which second electrodes are formed, said first substrate and second substrate disposed so as to face each other; and a plurality of cell spaces constituting pixels between said first substrate and second substrate. The first substrate comprises a plurality of first sheet members, each having a first electrode formed thereon. By disposing a cover substrate on said first sheet members, each with a partition wall therebetween, a plurality of subsheet formations comprising the plurality of cell spaces partitioned by the partition walls are formed, and the first electrodes are connected in between adjacent subsheet formations.
    Type: Application
    Filed: April 14, 2011
    Publication date: May 10, 2012
    Inventors: Koichi Hirano, Masami Nakagawa, Seiichi Nakatani
  • Patent number: 8143617
    Abstract: A semiconductor device having semiconductor elements disposed with higher density and a method for manufacturing the same are provided. An image display device employing the semiconductor device is also provided. A semiconductor device comprises a resin film having a through hole; and a semiconductor element comprising a gate electrode disposed on the inner wall of the through hole, an insulating layer that covers the gate electrode within the through hole, an organic semiconductor disposed on the insulating layer within the through hole, and a source electrode and a drain electrode which are electrically connected to the organic semiconductor.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: March 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Yamashita, Seiichi Nakatani
  • Patent number: 8097958
    Abstract: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: January 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Susumu Sawada, Seiichi Nakatani, Seiji Karashima, Takashi Kitae
  • Publication number: 20120001173
    Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The resin film comprises an opening formed by a laser irradiation therein, and also an electroconductive member which is in contact with the surface of the semiconductor structure portion is disposed within the opening of the resin film.
    Type: Application
    Filed: February 2, 2010
    Publication date: January 5, 2012
    Inventors: Takeshi Suzuki, Kenichi Hotehama, Seiichi Nakatani, Koichi Hirano, Tatsuo Ogawa
  • Patent number: 8071425
    Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217).
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: December 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Takashi Kitae, Yoshihisa Yamashita, Takashi Ichiryu, Seiji Karashima
  • Publication number: 20110293874
    Abstract: The hybrid substrate of the present invention comprises a ceramic substrate assembly composed of a plurality of ceramic substrates, insulating resin layers disposed respectively on both surfaces of the ceramic substrate assembly such that they are opposed to each other, each of the insulating resin layers being made at least of a reinforcing material and a resin, and a metal layer disposed on each of the insulating resin layers. In particular, the hybrid substrate of the present invention comprises the plurality of ceramic substrates which are in the form of a tile arrangement along the same plane positioned between the opposed insulating resin layers.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Takashi TOYOOKA, Hiroshi OKADA, Shigetoshi SEGAWA, Seiichi NAKATANI