Patents by Inventor Seiichi Uchida

Seiichi Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961473
    Abstract: A display device includes a pixel, wherein the pixel has a driving transistor, a monitoring transistor connected to the driving transistor, and a resistor provided in the pixel, and having one end connected between the driving transistor and the monitoring transistor, and the display device is capable of detecting a temperature of the pixel in accordance with a value of current that flows through the resistor and the monitoring transistor.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: April 16, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Seiichi Uchida
  • Publication number: 20240103311
    Abstract: Provided are a liquid crystal panel which has good visibility and in which a decrease in the display quality is sufficiently suppressed, and a head mounted display and a liquid crystal display device using the same. The liquid crystal panel includes a liquid crystal layer, a spacer, and a light-shielding section between a first substrate a second substrate facing the first substrate. The light-shielding section includes column-direction light-shielding sections arranged in a column direction and shielding parts between the pixels aligned in a row direction from light, and row-direction light-shielding sections arranged in the row direction and shielding parts between the pixels aligned in the column direction from light. The row-direction light-shielding sections include one that includes a first light-shielding section including an arrangement region of the spacer and a second light-shielding section adjacent to the first light-shielding section in the column direction.
    Type: Application
    Filed: August 14, 2023
    Publication date: March 28, 2024
    Inventors: Seiichi UCHIDA, Kuniaki OKADA, Keisuke YOSHIDA
  • Patent number: 11887541
    Abstract: A display device includes: a plurality of scanning lines; a plurality of data lines; a plurality of light-emission control lines; a plurality of pixel circuits each including a light-emitting element; a scanning line drive circuit that drives the scanning lines based on a first clock signal; a data line drive circuit that drives the data lines; a light-emission control line drive circuit that drives the light-emission control lines based on a second clock signal; and a display control circuit that outputs at least the first and second clock signals. The display control circuit classifies a frame period into a scanning period and a pause period, and during the pause period, the display control circuit stops the first clock signal and makes a frequency of the second clock signal lower than that during the scanning period. This further reduces the power consumption of the display device that performs low-frequency driving.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 30, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Seiichi Uchida
  • Publication number: 20230395023
    Abstract: A display device includes a pixel, wherein the pixel has a driving transistor, a monitoring transistor connected to the driving transistor, and a resistor provided in the pixel, and having one end connected between the driving transistor and the monitoring transistor, and the display device is capable of detecting a temperature of the pixel in accordance with a value of current that flows through the resistor and the monitoring transistor.
    Type: Application
    Filed: November 27, 2020
    Publication date: December 7, 2023
    Inventor: SEIICHI UCHIDA
  • Publication number: 20230375889
    Abstract: An active matrix substrate includes a substrate that is transparent, and a plurality of pixels positioned on the substrate. Each pixel includes a thin-film transistor (TFT) positioned on the substrate, a first color filter layer disposed on the substrate so as to cover the TFT, a contact hole being provided in the first color filter layer, a pixel electrode that is positioned on a bottom face and a side face of the contact hole, and on the first color filter layer, and that is electrically connected to the TFT via the contact hole, and a second color filter layer disposed within the contact hole.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 23, 2023
    Inventors: Seiichi UCHIDA, Kiyoshi MINOURA, Kuniaki OKADA, Hiromi KATOH, Keisuke YOSHIDA
  • Publication number: 20230274698
    Abstract: A display device includes: a plurality of scanning lines; a plurality of data lines; a plurality of light-emission control lines; a plurality of pixel circuits each including a light-emitting element; a scanning line drive circuit that drives the scanning lines based on a first clock signal; a data line drive circuit that drives the data lines; a light-emission control line drive circuit that drives the light-emission control lines based on a second clock signal; and a display control circuit that outputs at least the first and second clock signals. The display control circuit classifies a frame period into a scanning period and a pause period, and during the pause period, the display control circuit stops the first clock signal and makes a frequency of the second clock signal lower than that during the scanning period. This further reduces the power consumption of the display device that performs low-frequency driving.
    Type: Application
    Filed: August 3, 2020
    Publication date: August 31, 2023
    Inventor: Seiichi UCHIDA
  • Publication number: 20230186847
    Abstract: In a display device including scanning lines, light emission control lines, data lines, pixel circuits, and a drive circuit that drives the scanning lines, the light emission control lines, and the data lines, the pixel circuit includes a light-emitting element and a drive transistor that controls the amount of current flowing through the light-emitting element. The drive circuit has a monitoring mode, and during a frame period in the monitoring mode, the drive circuit sets non-light-emission periods, which are sequentially delayed and have the same length, for rows of the pixel circuits, selects a row to be measured from among the rows of the pixel circuits as a monitoring row, sets a monitoring period that partially overlaps a non-light-emission period of the monitoring row, and measures characteristics of light-emitting elements or drive transistors in pixel circuits in the monitoring row during the monitoring period.
    Type: Application
    Filed: October 23, 2019
    Publication date: June 15, 2023
    Inventor: Seiichi UCHIDA
  • Patent number: 10768496
    Abstract: An array board 11b includes a gate line 19, a TFT 17, a pixel electrode 18, a display pixel PX, and a second interlayer insulation film 27. The TFT 17 includes a gate electrode 17a formed from a part of the gate line 19, a channel section 17d formed from an oxide semiconductor film 24, a source section 17b connected to one end of the channel section 17d, and a drain section 17c connected to another end of the channel section 17d and formed from the oxide semiconductor film 24 having resistance lower than the channel section 17d. The pixel electrode 18 is connected to the drain section 17c. The display pixel PX includes the TFT 17 and the pixel electrode 18. The second interlayer insulation film 27 has a second hole in a position overlapping the pixel electrode and the drain section 17c and not overlapping the gate electrode 17a.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: September 8, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiichi Uchida, Kuniaki Okada, Naoki Ueda, Takahiro Sasaki
  • Patent number: 10698283
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of columnar spacers. The pixel arrangement is a stripe arrangement including red, green and blue pixel columns. The first substrate includes TFTs, one for each pixel, wherein each TFT includes an oxide semiconductor layer. The second substrate includes a color filter layer and a light-blocking layer. The light-blocking layer includes a plurality of first shading portions extending along the column direction, and a plurality of second shading portions extending along the row direction. Each of the columnar spacers is aligned with one of the second shading portions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 30, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kuniaki Okada, Seiichi Uchida
  • Publication number: 20200019004
    Abstract: A liquid crystal display device for head-mounted displays includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of columnar spacers. The first substrate has a TFT provided in each pixel, a plurality of gate bus lines, and a plurality of source bus lines. The TFT includes an oxide semiconductor layer. Each columnar spacer is in contact with both of the first substrate and the second substrate. The second substrate includes a light shielding layer, the light shielding layer including first light shielding portions overlapping the gate bus lines or the source bus lines and second light shielding portions respectively overlapping the columnar spacers. Each columnar spacer is placed in one of the plurality of blue pixels. The second light shielding portions of the light shielding layer are placed so that, in those blue pixels in which the second light shielding portions exist, a decrease in aperture ratio ascribable to the second light shielding portions is 30% or less.
    Type: Application
    Filed: February 6, 2018
    Publication date: January 16, 2020
    Inventors: Seiichi UCHIDA, Kuniaki OKADA
  • Publication number: 20200004073
    Abstract: A liquid crystal display device (100A) includes a TFT substrate (10), a counter substrate (30), and a liquid crystal layer (50). The TFT substrate includes gate bus lines (GL) extending in a first direction and source bus lines (SL) extending in a second direction. The counter substrate includes a plurality of columnar spacers (40) defining a thickness of the liquid crystal layer. A surface of the TFT substrate on the liquid crystal layer side includes a plurality of first projections overlapping a plurality of gate bus lines to extend in the first direction, and protruding on the liquid crystal layer side, and a plurality of second projections overlapping a plurality of source bus lines to extend in the second direction and protruding toward the liquid crystal layer. The plurality of columnar spacers include a first columnar spacer (40a) supporting at least two projections among the plurality of first projections or at least two projections among the plurality of second projections on a top surface.
    Type: Application
    Filed: March 12, 2018
    Publication date: January 2, 2020
    Inventors: KUNIAKI OKADA, SEIICHI UCHIDA
  • Patent number: 10386684
    Abstract: A semiconductor device (100A) includes a thin film transistor (10), an inter-layer insulation layer (22) covering the thin film transistor, and a transparent conductive layer (24) formed on the inter-layer insulation layer. The metal oxide layer (16) of the thin film transistor includes a first portion (16a) overlapping the gate electrode (12) via a gate insulation layer (14) and a second portion (16b) not overlapping the gate electrode (12). The second portion (16b) crosses a different edge (e2) different from an edge (e1) of the drain electrode (18d) on a side of the first portion when viewed in the normal direction of the substrate (11). The inter-layer insulation layer has a contact hole (22a) disposed to overlap a part of the drain electrode (18d) and at least a part of the second portion (16b) of the metal oxide layer when viewed in the normal direction of the substrate.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 20, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kuniaki Okada, Seiichi Uchida, Naoki Ueda, Sumio Katoh
  • Patent number: 10386670
    Abstract: A first substrate of a display device includes a TFT provided for each pixel and including an oxide semiconductor layer. A second substrate includes a color filter layer and a light blocking layer. At least one of a first, second and third color filter included in the color filter layer has an average transmittance of 0.2% or less for visible light having a wavelength of 450 nm or less. In pixels provided with color filters having an average transmittance of 0.2% or less for visible light having a wavelength of 450 nm or less, the light blocking layer (a) includes a TFT shading portion extending along a channel length direction and having a width that is less than or equal to a length of the oxide semiconductor layer along a channel width direction; (b) includes a TFT shading portion extending along the channel width direction and having a width that is less than or equal to the length of the oxide semiconductor layer along the channel length direction; or (c) includes no TFT shading portion.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 20, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiichi Uchida, Kuniaki Okada, Naoki Ueda
  • Publication number: 20190179181
    Abstract: A first substrate of a liquid crystal display device includes a plurality of gate lines, a plurality of source lines, a TFT and a pixel electrode provided in each of the pixels, a first insulating layer covering the source lines, and a first alignment film. A second substrate includes a light-blocking layer, a plurality of columnar spacers, and a second alignment film. A drain electrode of the TFT is a transparent drain electrode formed from the same transparent conductive film as the pixel electrode. Each columnar spacer is arranged in an intersecting region where one of the gate lines and one of the source lines intersect with each other. The first insulating layer has first openings formed in the intersecting regions corresponding to at least some columnar spacers. A surface of the first substrate on a side of the liquid crystal layer has depressed portions that are defined by the first openings. Distal end portions of the at least some columnar spacers are located in the depressed portions.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 13, 2019
    Inventors: Seiichi UCHIDA, Kuniaki OKADA
  • Publication number: 20190121181
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of columnar spacers. The pixel arrangement is a stripe arrangement including red, green and blue pixel columns. The first substrate includes TFTs, one for each pixel, wherein each TFT includes an oxide semiconductor layer. The second substrate includes a color filter layer and a light-blocking layer. The light-blocking layer includes a plurality of first shading portions extending along the column direction, and a plurality of second shading portions extending along the row direction. Each of the columnar spacers is aligned with one of the second shading portions.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 25, 2019
    Inventors: KUNIAKI OKADA, SEIICHI UCHIDA
  • Patent number: 10243083
    Abstract: A semiconductor device (1001) includes: a thin film transistor (101) including an oxide semiconductor layer (16) including a channel region, and a source contact region and a drain contact region arranged on opposite sides of the channel region; an insulating layer arranged so as to cover the oxide semiconductor layer (16), the insulating layer having a contact hole (CH) through which the drain contact region is exposed; and a transparent electrode (24) to be in contact with the drain contact region in the contact hole (CH), wherein: as seen from a direction normal to the substrate, at least a part R of the drain contact region overlaps a gate electrode (12); and on an arbitrary cross section that extends in a channel width direction across the at least part (R) of the drain contact region, a width of the oxide semiconductor layer (16) is greater than a width of the gate electrode (12), and the gate electrode (12) is covered by the oxide semiconductor layer (16) with the gate insulating layer therebetween.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 26, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiichi Uchida, Kuniaki Okada
  • Publication number: 20190081076
    Abstract: An array substrate (thin film transistor substrate) 11b includes a source line (line) 20, a TFT (thin film transistor) 17 including a plurality of electrodes 17a, 17b, and 17c, and a line connector 31 made of light-transmitting conductive material and connected to the source line 20. At least a portion of the line connector 31 includes one of electrodes 17a, 17b, and 17c.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 14, 2019
    Inventors: Kuniaki OKADA, Seiichi UCHIDA, Naoki UEDA, Takahiro SASAKI
  • Patent number: 10197874
    Abstract: A first substrate (10) of a liquid crystal display device (100) includes a TFT (2) that includes an oxide semiconductor layer (2a). A second substrate (20) includes a color filter layer (22) and a light-shielding layer (21). The light-shielding layer has a first TFT light-shielding portion (21t1) for each row in at least a blue pixel column, and a second TFT light-shielding portion (21t2) every n rows (n represents an integer of 2 or more) in a pixel column in which at least one type of color filter other than blue color filters is provided, the second TFT light-shielding portion having a larger area than the first TFT light-shielding portion. A columnar spacer (40) is arranged so as not to overlap the first TFT light-shielding portion but to overlap the second TFT light-shielding portion.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 5, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kuniaki Okada, Seiichi Uchida
  • Publication number: 20180358469
    Abstract: A semiconductor device (1001) includes: a thin film transistor (101) including an oxide semiconductor layer (16) including a channel region, and a source contact region and a drain contact region arranged on opposite sides of the channel region; an insulating layer arranged so as to cover the oxide semiconductor layer (16), the insulating layer having a contact hole (CH) through which the drain contact region is exposed; and a transparent electrode (24) to be in contact with the drain contact region in the contact hole (CH), wherein: as seen from a direction normal to the substrate, at least a part R of the drain contact region overlaps a gate electrode (12); and on an arbitrary cross section that extends in a channel width direction across the at least part (R) of the drain contact region, a width of the oxide semiconductor layer (16) is greater than a width of the gate electrode (12), and the gate electrode (12) is covered by the oxide semiconductor layer (16) with the gate insulating layer therebetween.
    Type: Application
    Filed: November 14, 2016
    Publication date: December 13, 2018
    Inventors: Seiichi UCHIDA, Kuniaki OKADA
  • Publication number: 20180348560
    Abstract: An array board 11b includes a gate line 19, a TFT 17, a pixel electrode 18, a display pixel PX, and a second interlayer insulation film 27. The TFT 17 includes a gate electrode 17a formed from a part of the gate line 19, a channel section 17d formed from an oxide semiconductor film 24, a source section 17b connected to one end of the channel section 17d, and a drain section 17c connected to another end of the channel section 17d and formed from the oxide semiconductor film 24 having resistance lower than the channel section 17d. The pixel electrode 18 is connected to the drain section 17c. The display pixel PX includes the TFT 17 and the pixel electrode 18. The second interlayer insulation film 27 has a second hole in a position overlapping the pixel electrode and the drain section 17c and not overlapping the gate electrode 17a.
    Type: Application
    Filed: February 17, 2017
    Publication date: December 6, 2018
    Inventors: Seiichi UCHIDA, Kuniaki OKADA, Naoki UEDA, Takahiro SASAKI