Patents by Inventor Seiichi Uchida
Seiichi Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9341904Abstract: The TFT substrate (10) of this liquid crystal display device (100) includes: a TFT (11) which is provided for each pixel; an upper electrode (12) which is electrically connected to the TFT's drain electrode (11d); a lower electrode (13) which is arranged under the upper electrode; and a dielectric layer (14) which is arranged between the upper and lower electrodes. Its counter substrate (20) includes a counter electrode (21) which faces the upper electrode. The upper electrode has first and second regions (R1, R2) which have mutually different electrode structures, and a third region (R3) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion (12c) that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L1) that splits each pixel into two adjacent regions in a row direction.Type: GrantFiled: March 15, 2013Date of Patent: May 17, 2016Assignee: Sharp Kabushiki KaishaInventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Yutaka Takamaru, Kohhei Tanaka, Mitsuhiro Murata, Akira Shibazaki, Ken Kuboki
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Patent number: 9337213Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.Type: GrantFiled: March 29, 2013Date of Patent: May 10, 2016Assignee: Sharp Kabushiki KaishaInventors: Kazuatsu Ito, Yutaka Takamaru, Tadayoshi Miyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Patent number: 9336736Abstract: Provided is a liquid crystal display device with reduced power consumption employing a CS drive method. A CS driver (500) consists of a CS shift register (510) and a CS output portion (520). The CS shift register (510) outputs control signals (COUT(1) to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion (520) outputs auxiliary capacitance signals (CSS(1) to CSS(m)) in accordance with the control signals (COUT(1) to COUT(m)), respectively. An idle period (T2) is set following a scanning period (T1). During the idle period (T2), the CS driver (500) is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck2). The idle-period CS frequency (fcck2) is lower than a scanning-period CS frequency (fcck1).Type: GrantFiled: July 25, 2012Date of Patent: May 10, 2016Assignee: Sharp Kabushiki KaishaInventors: Kaoru Yamamoto, Seiji Kaneko, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
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Patent number: 9310911Abstract: A semiconductor layer for an active element included in each of a plurality of pixels in a display section is constituted by an oxide layer containing at least one element selected from the group consisting of In, Ga, and Zn. There is provided, for the display section, a liquid crystal panel's timing controller (13) configured to carry out control so that (i) a length of a first period during which image data is written is not more than twice that of the second period and/or (ii) one (1) frame period is longer than 16.7 msec.Type: GrantFiled: July 27, 2012Date of Patent: April 12, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Yasuhiro Sugita, Kazutoshi Kida, Shinji Yamagishi, Yuhji Yashiro, Hiroyuki Ogawa, Shigeyasu Mori, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru
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Patent number: 9276126Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.Type: GrantFiled: January 24, 2013Date of Patent: March 1, 2016Assignee: Sharp Kabushiki KaishaInventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
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Patent number: 9276127Abstract: This TFT substrate (100A) includes: a gate connecting layer (3a) formed on a substrate (1) out of a same conductive film as a gate electrode (3) or a transparent connecting layer (2a) formed on the substrate (1) out of a same conductive film as a first transparent electrode (2); an oxide layer (5z) which is formed on an insulating layer (4) and which includes at least one conductor region (5a); and a source connecting layer (6a) formed on the oxide layer (5z) out of a same conductor film as a source electrode (6s). The source connecting layer (6a) is electrically connected to either the gate connecting layer (3a) or the transparent connecting layer (2a) via the at least one conductor region (5a).Type: GrantFiled: June 11, 2013Date of Patent: March 1, 2016Assignee: Sharp Kabushiki KaishaInventors: Seiichi Uchida, Tadayoshi Miyamoto, Yasuyuki Ogawa, Yutaka Takamaru, Kazuatsu Ito, Takuya Matsuo, Shigeyasu Mori
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Patent number: 9261746Abstract: In order to suppress crosstalk between a pixel electrode and a source line to reduce flicker, an LCD device includes: gate lines 102 and source lines 105 which are provided in a grid pattern; pixel electrodes 111 arranged in a matrix pattern so as to correspond to intersections of the gate lines and the source lines; a transparent auxiliary capacitor electrode 109; and switching elements 121 configured to apply an image signal voltage supplied from the source line 105 to the pixel electrode 111 according to a scanning signal applied from the gate line 102. The switching element 121 is formed by using an oxide semiconductor layer 104, and the transparent auxiliary capacitor electrode 109 is provided between the source line 105 and the pixel electrode 111.Type: GrantFiled: August 3, 2012Date of Patent: February 16, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Yutaka Takamaru, Shigeyasu Mori
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Patent number: 9229284Abstract: A liquid crystal display device of the present invention is provided with: an array substrate (10) in which a pixel electrode (41), a TFT (20), and a storage capacitor element (30) are provided for each pixel (P); an opposite substrate (50) in which a plurality of common electrodes (59A, 59B) are provided for each pixel (P); a liquid crystal layer (81); and a driver circuit (4) that dividedly drives the liquid crystal layer (81) of each pixel (P) through each of the common electrodes (59A, 59B) by supplying a predetermined potential to each pixel electrode (41) and supplying different potentials to the respective common electrodes (59A, 59B) in each pixel (P). The liquid crystal display device according to the present invention has improved viewing angle dependency of the gamma characteristics, while increasing the aperture ratio of each pixel.Type: GrantFiled: April 13, 2012Date of Patent: January 5, 2016Assignee: SHARP KABUSHIKI KAISHAInventor: Seiichi Uchida
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Patent number: 9214533Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: GrantFiled: January 24, 2013Date of Patent: December 15, 2015Assignee: Sharp Kabushiki KaishaInventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Takuya Matsuo, Seiichi Uchida
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Publication number: 20150255491Abstract: An active matrix substrate (100) includes: a gate electrode (12) formed on a substrate; an oxide semiconductor layer (16); a source electrode (14); a drain electrode (15A); a drain connecting portion (15B) as an extended portion of the drain electrode (15A); a first transparent conductive layer (22, 24); and a second transparent conductive layer (26), wherein: the drain connecting portion (15B) is arranged close to the drain electrode (15A); and the drain electrode (15A) extends from a connecting portion thereof for connection with the oxide semiconductor layer (16), across an edge of the gate electrode (12), and to the drain connecting portion (15B), where a width of the drain electrode (15A) is smaller than a width of the drain connecting portion (15B).Type: ApplicationFiled: October 18, 2013Publication date: September 10, 2015Inventor: Seiichi Uchida
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Publication number: 20150243790Abstract: This TFT substrate (100A) includes: a gate connecting layer (3a) formed on a substrate (1) out of a same conductive film as a gate electrode (3) or a transparent connecting layer (2a) formed on the substrate (1) out of a same conductive film as a first transparent electrode (2); an oxide layer (5z) which is formed on an insulating layer (4) and which includes at least one conductor region (5a); and a source connecting layer (6a) formed on the oxide layer (5z) out of a same conductor film as a source electrode (6s). The source connecting layer (6a) is electrically connected to either the gate connecting layer (3a) or the transparent connecting layer (2a) via the at least one conductor region (5a).Type: ApplicationFiled: June 11, 2013Publication date: August 27, 2015Applicant: Sharp Kabushiki KaishaInventors: Seiichi Uchida, Tadayoshi Miyamoto, Yasuyuki Ogawa, Yutaka Takamaru, Kazuatsu Ito, Takuya Matsuo, Shigeyasu Mori
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Publication number: 20150200303Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8a) including portions formed on the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8a). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the interlayer insulating layer (8a) interposed between them. And the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of a same oxide film.Type: ApplicationFiled: June 12, 2013Publication date: July 16, 2015Inventors: Seiichi Uchida, Yasuyuki Ogawa, Tadayoshi Miyamoto, Kazuatsu Ito, Yutaka Takamaru, Makoto Nakazawa, Mitsunobu Miyamoto
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Patent number: 9035299Abstract: A TFT substrate (10A), which is semiconductor device of the present invention, has a first substrate (11), and a plurality of TFTs supported by the first substrate (11). Each TFT has an oxide semiconductor layer (22A) supported by the first substrate (11), an insulating layer (32A) formed on the oxide semiconductor layer (22A), a first electrode (12A) formed on the insulating layer (32A), and a second electrode (14A) and a third electrode (13A) connected to the oxide semiconductor layer (22A). The second electrode (14A) and the third electrode (13A) are formed of an oxide conductive layer in which the same oxide semiconductor film as the oxide semiconductor layer (22A) is given a reduced resistance.Type: GrantFiled: November 29, 2011Date of Patent: May 19, 2015Assignee: SHARP KABUSHIKI KAISHAInventor: Seiichi Uchida
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Publication number: 20150123117Abstract: A TFT substrate (100A) includes an oxide layer (15) which has a semiconductor region (5) and a conductor region (7) and in which the semiconductor region overlaps at least partially with a gate electrode (3a) with a first insulating layer (4) interposed between them, a protective layer (8) which covers the channel region of the semiconductor region, and a transparent electrode (9) which is arranged to overlap with at least a portion of the conductor region when viewed along a normal to the substrate (2). An end portion of the oxide layer is at least partially covered with the protective layer.Type: ApplicationFiled: April 26, 2013Publication date: May 7, 2015Applicant: Sharp Kabushshiki KaishaInventors: Kazuatsu Ito, Tadayoshi Miyamoto, Yasuyuki Ogawa, Seiichi Uchida
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Publication number: 20150084039Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.Type: ApplicationFiled: April 22, 2013Publication date: March 26, 2015Inventors: Yutaka Takamaru, Kazuatsu Ito, Tadayoshi Miyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Publication number: 20150053969Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.Type: ApplicationFiled: March 29, 2013Publication date: February 26, 2015Inventors: Kazuatsu Ito, Yutaka Takamaru, Tadayoshi MIiyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
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Publication number: 20150049290Abstract: The TFT substrate (10) of this liquid crystal display device (100) includes: a TFT (11) which is provided for each pixel; an upper electrode (12) which is electrically connected to the TFT's drain electrode (11d); a lower electrode (13) which is arranged under the upper electrode; and a dielectric layer (14) which is arranged between the upper and lower electrodes. Its counter substrate (20) includes a counter electrode (21) which faces the upper electrode. The upper electrode has first and second regions (R1, R2) which have mutually different electrode structures, and a third region (R3) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion (12c) that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L1) that splits each pixel into two adjacent regions in a row direction.Type: ApplicationFiled: March 15, 2013Publication date: February 19, 2015Inventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Yutaka Takamaru, Kohhei Tanaka, Mitsuhiro Murata, Akira Shibazaki, Ken Kuboki
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Publication number: 20150041800Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.Type: ApplicationFiled: January 24, 2013Publication date: February 12, 2015Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
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Publication number: 20140367677Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: ApplicationFiled: January 24, 2013Publication date: December 18, 2014Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Takuya Matsuo, Seiichi Uchida
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Publication number: 20140361295Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.Type: ApplicationFiled: January 24, 2013Publication date: December 11, 2014Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo