Patents by Inventor Seiji Inumiya
Seiji Inumiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10985104Abstract: A semiconductor device according to an embodiment includes a first electrode pad containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; an electrode layer containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; and a semiconductor layer provided between the first electrode pad and the electrode layer.Type: GrantFiled: August 15, 2018Date of Patent: April 20, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Seiji Inumiya, Kyoichi Suguro
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Publication number: 20190295957Abstract: A semiconductor device according to as embodiment includes a first electrode pad containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; an electrode layer containing copper as a main component and having a thickness equal to or more than 5 ?m and less than 50 ?m; and a semiconductor layer provided between the first electrode pad and the electrode layer.Type: ApplicationFiled: August 15, 2018Publication date: September 26, 2019Inventors: Seiji Inumiya, Kyoichi Suguro
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Publication number: 20190296138Abstract: A semiconductor apparatus according to the present embodiment is a semiconductor apparatus including a first nitride semiconductor layer including a first region having a first upper surface, a second region having a second upper surface parallel to the first upper surface, and a third region provided between the first region and the second region and having a third upper surface inclined with respect to the first upper surface and the second upper surface; a second nitride semiconductor layer including a fourth upper surface provided above the first upper surface, a fifth upper surface provided above the second upper surface, and a sixth upper surface provided above the third upper surface and being parallel to the third upper surface, the fourth upper surface being parallel to the first upper surface and being a +c face, the fifth upper surface parallel to the second upper surface and being a +c face, and the second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor lType: ApplicationFiled: August 31, 2018Publication date: September 26, 2019Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hiroaki HAYASHI, Seiji INUMIYA, Takashi ONIZAWA, Emiko INOUE
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Patent number: 10381471Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer, a gate electrode, an aluminum oxynitride layer provided between the gate electrode and the second nitride semiconductor layer, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode electrically connected to the first nitride semiconductor layer, a first aluminum nitride layer provided on the second nitride semiconductor layer between the first electrode and the aluminum oxynitride layer, and a second aluminum nitride layer provided on the second nitride semiconductor layer between the second electrode and the aluminum oxynitride layer. The second nitride semiconductor layer has an electron affinity lower than that of the first nitride semiconductor layer. A second electrode sandwiches the gate electrode together with the first electrode.Type: GrantFiled: March 17, 2017Date of Patent: August 13, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Seiji Inumiya
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Patent number: 10096619Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.Type: GrantFiled: September 6, 2016Date of Patent: October 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsunehiro Ino, Shosuke Fujii, Seiji Inumiya
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Publication number: 20180069112Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer, a gate electrode, an aluminum oxynitride layer provided between the gate electrode and the second nitride semiconductor layer, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode electrically connected to the first nitride semiconductor layer, a first aluminum nitride layer provided on the second nitride semiconductor layer between the first electrode and the aluminum oxynitride layer, and a second aluminum nitride layer provided on the second nitride semiconductor layer between the second electrode and the aluminum oxynitride layer. The second nitride semiconductor layer has an electron affinity lower than that of the first nitride semiconductor layer. A second electrode sandwiches the gate electrode together with the first electrode.Type: ApplicationFiled: March 17, 2017Publication date: March 8, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Seiji INUMIYA
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Publication number: 20160372478Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Shosuke FUJII, Seiji INUMIYA
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Patent number: 9362487Abstract: According to one embodiment, a ferroelectric memory includes a semiconductor layer, an interfacial insulating film formed on the semiconductor layer, a ferroelectric film formed on the interfacial insulating film, and a gate electrode formed on the ferroelectric film, wherein the ferroelectric film is a film which includes a metal that is hafnium (Hf) or zirconium (Zr) and oxygen as the main components and to which an element selected from the group consisting of silicon (Si), magnesium (Mg), aluminum (Al).Type: GrantFiled: September 6, 2013Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Seiji Inumiya, Yoshio Ozawa, Koji Yamakawa, Atsuko Sakata, Masayuki Tanaka, Junichi Wada
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Publication number: 20150179657Abstract: A semiconductor storage device is provided with a semiconductor channel region; a first insulating layer including an oxide film disposed in contact with the semiconductor channel region, an yttrium oxide containing film disposed on the oxide film, and a hafnium oxide film having an orthorhombic phase III structure disposed on the yttrium oxide containing film; and a control electrode disposed on the first insulating layer.Type: ApplicationFiled: September 9, 2014Publication date: June 25, 2015Inventor: Seiji INUMIYA
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Publication number: 20140070290Abstract: According to one embodiment, a ferroelectric memory includes a semiconductor layer, an interfacial insulating film formed on the semiconductor layer, a ferroelectric film formed on the interfacial insulating film, and a gate electrode formed on the ferroelectric film, wherein the ferroelectric film is a film which includes a metal that is hafnium (Hf) or zirconium (Zr) and oxygen as the main components and to which an element selected from the group consisting of silicon (Si), magnesium (Mg), aluminum (Al).Type: ApplicationFiled: September 6, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Seiji INUMIYA, Yoshio Ozawa, Koji Yamakawa, Atsuko Sakata, Masayuki Tanaka, Junichi Wada
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Publication number: 20140070289Abstract: According to one embodiment, a ferroelectric memory includes a gate insulation film formed on a semiconductor substrate, a ferroelectric film formed on the gate insulation film, and a control electrode formed on the ferroelectric film. The ferroelectric film is a film containing a metal, which is hafnium or zirconium, and oxygen, and contains an element other than the metal at a concentration lower than a concentration of the metal.Type: ApplicationFiled: September 3, 2013Publication date: March 13, 2014Inventors: Masayuki TANAKA, Junichi WADA, Yoshio OZAWA, Koji YAMAKAWA, Seiji INUMIYA, Atsuko SAKATA
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Patent number: 8461006Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.Type: GrantFiled: March 30, 2012Date of Patent: June 11, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Seiji Inumiya
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Patent number: 8435858Abstract: A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by using wet etching and subsequently oxidizing a surface of the substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the substrate on the surface of the substrate; forming a second insulating film containing aluminum and another metal element on the first insulating film; forming a high-k insulating film containing at least one of hafnium and zirconium on the second insulating film; forming a metal film on the high-k insulating film; and conducting heat treatment to react the first insulating film and the second insulating film, thereby forming a third insulating film made of a mixture containing aluminum, the another metal element, the constituent element of the substrate, and oxygen.Type: GrantFiled: October 27, 2011Date of Patent: May 7, 2013Assignee: Kabshiki Kaisha ToshibaInventors: Seiji Inumiya, Tomonori Aoyama
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Patent number: 8404575Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.Type: GrantFiled: December 6, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Seiji Inumiya
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Publication number: 20120184096Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.Type: ApplicationFiled: March 30, 2012Publication date: July 19, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Masato KOYAMA, Yoshinori TSUCHIYA, Seiji INUMIYA
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Patent number: 8198159Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.Type: GrantFiled: March 24, 2008Date of Patent: June 12, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya
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Patent number: 8198155Abstract: A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate.Type: GrantFiled: January 26, 2010Date of Patent: June 12, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Ikeno, Tomonori Aoyama, Kazuaki Nakajima, Seiji Inumiya, Takashi Shimizu, Takuya Kobayashi
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Patent number: 8183641Abstract: A silicon oxynitride film is formed on entire surface of a semiconductor substrate, a lanthanum oxide film is formed on the silicon oxynitride film and the lanthanum oxide film is removed from a pMOS region. Then, a nitrided hafnium silicate film serving as a highly dielectric film is formed on the entire surface, an aluminum-containing titanium nitride film is formed, a polysilicon film is formed, and the stacked films are patterned into a gate electrode configuration. Next, impurities are introduced into a source/drain region, and an annealing for activating the impurities is utilized to diffuse the aluminum included in the aluminum-containing titanium nitride film to the interface between the silicon oxynitride film and the nitrided hafnium aluminum silicate film in the pMOS region.Type: GrantFiled: November 25, 2009Date of Patent: May 22, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Tomonori Aoyama
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Patent number: 8168499Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.Type: GrantFiled: April 23, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Seiji Inumiya
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Publication number: 20120077336Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.Type: ApplicationFiled: December 6, 2011Publication date: March 29, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Akio KANEKO, Seiji INUMIYA