Patents by Inventor Seiji Inumiya

Seiji Inumiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050158932
    Abstract: A method of manufacturing a semiconductor device, comprises: providing a gate insulation layer of a high dielectric constant containing a metal element on a surface of a semiconductor substrate, part of which becoming a channel; providing a first conductive layer containing a silicon element on the surface of said gate insulation layer, said first conductive layer being a gate electrode; and introducing nitrogen or oxygen onto an interface between said gate insulation layer and said first conductive layer by executing a thermal treatment upon said semiconductor substrate in a atmosphere containing a nitriding agent or an oxidizing agent.
    Type: Application
    Filed: November 24, 2004
    Publication date: July 21, 2005
    Inventors: Seiji Inumiya, Akio Kaneko, Motoyuki Sato, Katsuyuki Sekine, Kazuhiro Eguchi, Yoshitaka Tsunashima
  • Publication number: 20050110101
    Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.
    Type: Application
    Filed: August 27, 2004
    Publication date: May 26, 2005
    Inventors: Akio Kaneko, Kazuhiro Eguchi, Seiji Inumiya, Katsuyuki Sekine, Motoyuki Sato
  • Publication number: 20050067704
    Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
    Type: Application
    Filed: December 18, 2003
    Publication date: March 31, 2005
    Inventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
  • Publication number: 20050064667
    Abstract: A semiconductor device manufacturing method comprises: forming a first nitride film on a semiconductor substrate; forming a first oxide film between said semiconductor substrate and said nitride film and forming a second oxide film on said nitride film; forming a second nitride film or an oxide and nitride film on said first nitride film by nitriding said second oxide film; and forming a gate electrode on a gate insulative film including said first oxide film, said first nitride film, and said second nitride film or said oxide and nitride film.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 24, 2005
    Inventors: Daisuke Matsushita, Koichi Muraoka, Seiji Inumiya, Koichi Kato, Kazuhiro Eguchi, Mariko Takayanagi, Yasushi Nakasaki
  • Patent number: 6844234
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20050006674
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Application
    Filed: August 5, 2004
    Publication date: January 13, 2005
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20040259297
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
    Type: Application
    Filed: July 20, 2004
    Publication date: December 23, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
  • Publication number: 20040235254
    Abstract: There is disclosed a method of manufacturing a semiconductor device, which comprises forming a film containing metal elements and silicon elements on a semiconductor substrate, exposing the semiconductor substrate to an atmosphere containing an oxidant to form a silicon dioxide film at the interface between the semiconductor substrate and the film containing metal elements and silicon elements, and nitriding the film containing metal elements and silicon elements after forming the silicon dioxide film.
    Type: Application
    Filed: March 12, 2004
    Publication date: November 25, 2004
    Inventors: Seiji Inumiya, Kazuhiro Eguchi
  • Publication number: 20040195636
    Abstract: A semiconductor device comprises a semiconductor region including silicon, and an insulating film including silicon, oxygen, nitrogen, and helium, the dielectric film provided on the semiconductor region, and the dielectric film having a concentration distribution with respect to a film thickness direction, the concentration distribution having a maximal value of concentration of the helium in a surface portion on the semiconductor region side and a maximal value of concentration of the nitrogen in a surface portion on a side opposite to the semiconductor region.
    Type: Application
    Filed: February 25, 2004
    Publication date: October 7, 2004
    Inventors: Katsuyuki Sekine, Seiji Inumiya, Ichiro Mizushima
  • Patent number: 6787827
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
  • Patent number: 6784508
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Patent number: 6664592
    Abstract: A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom and side surface the gate insulator film is formed, and an upper portion protruding a surface of said semiconductor substrate, and source region and a drain region formed on a surface of the semiconductor substrate in such a way as to sandwich the gate electrode. A thickness of the upper portion of the gate electrode protruding the surface of the semiconductor substrate is equal to or greater than twice a thickness of the lower portion of the gate electrode buried in the groove.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: December 16, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Tomohiro Saito, Atsushi Yagishita, Katsuhiko Hieda, Toshihiko Iinuma
  • Publication number: 20030218223
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. A semiconductor device of one of several disclosed embodiments comprises a semiconductor layer having a source region and a drain region, and a gate insulating film provided on the semiconductor layer between the source region and the drain region. The gate insulating film comprising an oxide including a metal element and further includes at least one element selected from the group consisting of nitrogen and aluminum as a first element. The content of the first element is relatively higher at both ends near the source region and the drain region than at a center of the gate insulating film. A gate electrode is provided on the gate insulating film.
    Type: Application
    Filed: February 26, 2003
    Publication date: November 27, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira Nishiyama, Seiji Inumiya
  • Publication number: 20030127640
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Application
    Filed: March 21, 2002
    Publication date: July 10, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20030107088
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.
    Type: Application
    Filed: December 30, 2002
    Publication date: June 12, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Inumiya, Tomohiro Saito, Atsushi Yagishita, Katsuhiko Hieda, Toshihiko Iinuma
  • Patent number: 6515338
    Abstract: A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: February 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Tomohiro Saito, Atsushi Yagishita, Katsuhiko Hieda, Toshihiko Iinuma
  • Publication number: 20020117698
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
    Type: Application
    Filed: April 26, 2002
    Publication date: August 29, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
  • Publication number: 20020090830
    Abstract: A semiconductor device is provided in which a lowering in the breakdown voltage of a gate insulating film (nitrided silicon oxide film) in a boundary region between the upper-end corner portion of the side wall of an element isolating groove and a silicon substrate in the end portion of an element forming region which is formed in contact therewith can be suppressed without causing an increase in the number of steps (time for effecting the steps).
    Type: Application
    Filed: March 8, 2002
    Publication date: July 11, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Inumiya, Yoshio Ozawa
  • Patent number: 6403997
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: June 11, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
  • Patent number: 6383856
    Abstract: A semiconductor device is provided in which a lowering in the breakdown voltage of a gate insulating film (nitrided silicon oxide film) in a boundary region between the upper-end corner portion of the side wall of an element isolating groove and a silicon substrate in the end portion of an element forming region which is formed in contact therewith can be suppressed without causing an increase in the number of steps (time for effecting the steps).
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: May 7, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Yoshio Ozawa