Abstract: One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer.

Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: A method of producing a semiconductor device according to an embodiment of the present invention includes: step (C) of forming an oxide semiconductor layer of a plurality of thin film transistors on a gate dielectric layer; step (F) of forming an aperture in an interlevel dielectric layer, the aperture being located between an active region and a plurality of terminal portions and extending through the interlevel dielectric layer; and step (G) of, after step (F), forming an upper conductive portion on the interlevel dielectric layer. In step (C), a protection layer made of the same oxide semiconductor film as the oxide semiconductor layer is formed above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions. In step (F), the aperture is formed so as to overlap the protection layer.

Abstract: A method includes a conductive film forming process of forming a conductive film 51 covering a gate insulation film IS and a semiconductor film 42, the gate insulation film 45 covering a gate electrode 37G and a gate line 35G formed on a glass substrate 32 and the semiconductor film 42 formed on the gate insulation film 45 while overlapping the gate electrode 37G, a first etching process of etching the conductive film 51 and forming a source conductive film 46S connected to the semiconductor film 42 and a drain conductive film 46D connected to the semiconductor film 42, a resist forming process performed after the first etching process and forming a resist 53R covering the semiconductor film 42, the source conductive film 46S, and the drain conductive film 46D, and a second etching process performed after the resist forming process and performing etching for removing the conductive film 51 while using the resist 53R as a mask.

Abstract: A thin film transistor (TFT) 11 includes a gate electrode 11a, a channel section 11d formed of an oxide semiconductor film 17, a source electrode 11b connected to one end of the channel section 11d, and a drain electrode 11c connected to another end of the channel section 11d, and the oxide semiconductor film 17 is an oxide semiconductor containing at least gallium and indium and an atomic ratio Ga/(Ga+In) is from 1/4.2 to 1/3.3.

Abstract: A semiconductor device includes: a first thin film transistor (101) including a crystalline silicon semiconductor layer (13); and a second thin film transistor (102) including an oxide semiconductor layer (23).

Abstract: An array board includes a glass substrate, gate insulating film, a first interlayer insulating film, a gate insulating film inclined section, a first interlayer insulating film inclined section, and an overlapping portion. The glass substrate includes a display area and a non-display area. The gate insulating film and the first interlayer insulating film include a gate insulating film voided area and a first interlayer insulating film voided area in the non-display area. The gate insulating film inclined section and the interlayer insulating film inclined section are inclined from boundaries with the gate insulating film voided area and the first interlayer insulating film voided area and angled relative to a plate surface of the glass substrate. The overlapping portion overlaps the gate insulating film voided area, the first interlayer insulating film voided area, the gate insulating film inclined section, and the first interlayer insulating film inclined section.

Abstract: An array board includes input terminals, a first interlayer insulating film, a first planarization film, terminal lines, a second planarization film, and protective members. A first interlayer insulating film edge section and a first planarization film edge section are disposed between the input terminals and the display area. The terminal lines in a layer upper than the first planarization film and extending to cross the first interlayer insulating film edge section and the first planarization film edge section are connected to the input terminals. The second planarization film in a layer upper than the terminal lines includes a second planarization film edge section disposed closer to the input terminals relative to the first interlayer insulating edge section and the first planarization film edge section. The protective members in a layer upper than the second planarization film cover sections of the terminals lines not overlapping the second planarization film, respectively.

Abstract: An array board includes a glass substrate, input terminals, a gate insulating film including a gate insulating film edge section, a first interlayer insulating film including a first interlayer insulating film edge section, a first planarization film, and terminal lines. At least parts of the gate insulating film edge section and the first interlayer insulating film edge section are angled relative to a plate surface of the glass substrate with an angle of slope equal to or smaller than 35°. The first planarization film includes a first planarization film edge section angled relative to the plate surface with an angle of slope smaller than the angle of slope of the gate insulating film edge section. The terminal lines are disposed to cross the gate insulating film edge section, the first interlayer insulating film edge section, and the first planarization film edge section and connected to the input terminals.

Abstract: One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer.

Abstract: An off-leakage current of a photodiode is reduced in a photoelectric conversion device. A photoelectric conversion device (100) includes: an oxide semiconductor layer (5) provided on a substrate (1); a passivation film (6) and a planarizing film (7) which are stacked on the oxide semiconductor layer; and a photodiode (9) including a lower electrode (91), a photoelectric conversion layer (92), and an upper electrode (93). The lower electrode is connected to a source electrode (4) via a contact hole provided in the passivation film and the planarizing film. No photoelectric conversion layer is provided directly above the contact hole.

Abstract: A semiconductor device (1001) includes a thin-film transistor (101) including a gate electrode (3), an oxide semiconductor layer (7), a gate insulating layer (5), a source electrode (9s), and a drain electrode (9d); a metal oxide layer (8) including a conductor region (70c) and formed from an oxide film from which the oxide semiconductor layer (7) is also formed; an interlayer insulating layer (13) covering the thin-film transistor and the metal oxide layer (8); and a transparent conductive layer (15) disposed on the interlayer insulating layer and electrically connected to the drain electrode, wherein the oxide semiconductor layer (7) and the metal oxide layer (8) contain indium, tin, and zinc, and the transparent conductive layer (15) overlaps at least a portion of the conductor region (70c) with the interlayer insulating layer (13) therebetween.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: An active matrix substrate (1001) includes a connecting portion (101). The connecting portion. (101) includes a lower conductive layer supported by a substrate; a first insulating layer formed so as to cover the lower conductive layer (2) and having a contact hole (6p) that exposes a part of the lower conductive layer (2); a bottom conductive film (4) that is disposed in the contact hole (6p) and covers at least a part of the exposed part of the lower conductive layer (2), the exposed part being exposed by the contact hole (6p); a second insulating layer (9) that is formed on the first insulating layer (6) and in the contact hole (6p), is in contact with the bottom conductive film (4) in the contact hole (6p), and has an opening (9p) that exposes a part of the bottom conductive film (4); and an upper conductive layer (8) that is disposed on the second insulating layer (9) and in the opening (9p) and is in contact with the bottom conductive film (4) in the opening (9p).

Abstract: A semiconductor device (100A) includes a substrate (11); a TFT (10A) supported on the substrate, the TFT including an oxide semiconductor layer (16); an organic insulating layer (24) covering the TFT; a lower layer electrode (32) on the organic insulating layer; a dielectric layer (34) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode (36) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×1021 atoms/cm3 or less.

Abstract: A semiconductor device (1001) includes a thin-film transistor (101) including a gate electrode (3), an oxide semiconductor layer (7), a gate insulating layer (5), a source electrode (9s), and a drain electrode (9d); a metal oxide layer (8) including a conductor region (70c) and formed from an oxide film from which the oxide semiconductor layer (7) is also formed; an interlayer insulating layer (13) covering the thin-film transistor and the metal oxide layer (8); and a transparent conductive layer (15) disposed on the interlayer insulating layer and electrically connected to the drain electrode, wherein the oxide semiconductor layer (7) and the metal oxide layer (8) contain indium, tin, and zinc, and the transparent conductive layer (15) overlaps at least a portion of the conductor region (70c) with the interlayer insulating layer (13) therebetween.

Abstract: A shift of a threshold voltage of a thin film transistor upon X-ray irradiation is suppressed. An imaging panel having a plurality of pixels, for picking up scintillation light obtained by converting X-ray projected from an X-ray source, with use of a scintillator, includes photodiodes 15, TFTs 14, and an organic film 43. The photodiodes 15 are provided at the pixels, respectively, for receiving the scintillation light and converting the same into charges. The TFTs 14 are provided at the pixels, respectively, for reading the charges obtained through the conversion by the photodiodes 15. Each TFT 14 includes an oxide semiconductor layer 142, a gate electrode 141, as well as a source electrode 143S and a drain electrode 143D formed on a part of the oxide semiconductor layer 142.

Abstract: Provided is an imaging panel and an imaging device with which the amount of irradiated X-ray can be reduced, and at the same time, the threshold voltage of a TFT during X-ray irradiation can be prevented from shifting. The imaging panel includes an imaging part that includes a plurality of pixels 13 that generate charges based on X-ray projected from an X-ray source, and a thin film transistor 14 for reading out the charges generated at the pixel 13. The thin film transistor 14 has a gate 141 and an oxide semiconductor layer 142, as well as a source 143S and a drain 143D formed on a part of the oxide semiconductor layer 142 by wet etching with respect to a metal film formed on the oxide semiconductor layer 142. The oxide semiconductor layer 142 contains indium, tin, gallium, and oxygen.

Abstract: A semiconductor device includes an oxide semiconductor film, a first insulating film, and a second insulating film. The oxide semiconductor film is made of oxide semiconductor material. The oxide semiconductor film includes a low resistance portion having an electrical resistance lower than another portion. The low resistance portion is separated from the other portion. The first insulating film is formed in an upper layer relative to the oxide semiconductor film. The first insulating film includes a hole at a position overlapping the low resistance portion. The second insulating film is formed in an upper layer relative to the first insulating film. The second insulating film and contains hydrogen.