Patents by Inventor Seiji Kaneko

Seiji Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170184893
    Abstract: A semiconductor device includes a substrate, a first thin film transistor supported on the substrate and having a first active layer that primarily contains a first oxide semiconductor, and second thin film transistor supported on the substrate and having a second active layer that primarily contains a second oxide semiconductor with a higher mobility than the first oxide semiconductor. The first active layer and the second active layer are positioned on the same insulating layer and contact the same insulating layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: June 29, 2017
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takao SAITOH, Seiji KANEKO, Yohsuke KANZAKI, Yutaka TAKAMARU, Keisuke IDE, Takuya MATSUO
  • Patent number: 9690155
    Abstract: A TFT substrate (100A) of a liquid crystal display panel includes: an organic interlayer insulating layer (24) covering a TFT; a first transparent electrically-conductive layer (25) provided in the first region of a surface of the organic interlayer insulating layer (24); and an inorganic dielectric layer (26) covering the first transparent electrically-conductive layer (25) and provided in a second region of the surface of the organic interlayer insulating layer (24) which is different from the first region, the inorganic dielectric layer (26) containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer (24) is not less than 3.45 nm and not more than 5.20 nm.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 27, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takamaru, Seiji Kaneko, Takao Saitoh, Yohsuke Kanzaki, Keisuke Ide, Hiroshi Matsukizono
  • Publication number: 20170162602
    Abstract: A semiconductor device (100) includes, on a substrate, a plurality of oxide semiconductor TFTs including a first gate electrode (12), a first insulating layer (20) which is in contact with the first gate electrode, an oxide semiconductor layer (16) arranged so as to oppose the first gate electrode via the first insulating layer, and a source electrode (14) and a drain electrode (15) which are connected with the oxide semiconductor layer, and an organic insulating layer (24) covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT (5A) which is covered with the organic insulating layer and a second TFT (5B) which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode (17) arranged so as to oppose the oxide semiconductor layer via a second insulating layer (22), when viewed in a direction normal to the substrate, the second gate electrode (17) being arranged so as to overlap with at least
    Type: Application
    Filed: August 26, 2014
    Publication date: June 8, 2017
    Inventors: Takao SAITOH, Seiji KANEKO, Yohsuke KANZAKI, Yutaka TAKAMARU, Keisuke IDE, Takuya MATSUO, Shigeyasu MORI, Hiroshi MATSUKIZONO
  • Publication number: 20170125452
    Abstract: A semiconductor device (100) includes a substrate (11), a first TFT (10), and a second TFT (20). The first TFT includes a first semiconductor layer (12) that is supported by the substrate, a first gate electrode (14) that is formed on the first semiconductor layer and overlaps with the first semiconductor layer with a first gate insulating layer (13) interposed therebetween, a first insulating layer (16) that covers the first gate electrode, and a first source electrode (17s) and a first drain electrode (17d) that are formed on the first insulating layer and are connected to the first semiconductor layer.
    Type: Application
    Filed: June 9, 2015
    Publication date: May 4, 2017
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Keisuke IDE, Takao SAITOH, Yohsuke KANZAKI, Yutaka TAKAMARU, Seiji KANEKO, Hiroshi MATSUKIZONO, Tadayoshi MIYAMOTO
  • Patent number: 9595232
    Abstract: Provided are: a liquid crystal display device capable of rapidly discharging an image signal which is held in a pixel formation portion, when a power supply thereof is turned off; and a driving method of the liquid crystal display device. If the liquid crystal display device shifts to an off-sequence mode, then a data signal Vd with a potential Vdoff1 corresponding to a shift amount ?V3 lowered by a coupling effect of a parasitic capacitance formed between a gate terminal and drain terminal of a thin film transistor (12) is applied to a signal line SL. When a scanning signal Vg turns to a high level, the data signal Vd applied to the signal line SL is written into the pixel formation portion (11), and a potential of a pixel signal Vpix becomes the Vdoff1. When the scanning signal Vg falls to a ground potential GND after an elapse of a period t1, the potential of the pixel signal Vpix is lowered by a shift amount ?V3, and accordingly, the potential of the pixel signal Vpix becomes the ground potential GND.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: March 14, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Seiji Kaneko
  • Patent number: 9581843
    Abstract: At the time of partial drive, the levels of voltages applied to data lines SL1 to SLn are switched according to a rewrite frequency set for each region of a display screen. For example, in a still-image display region with a relatively low rewrite frequency, the levels of the voltages applied to the data lines SL1 to SLn are set to be higher than those for a moving-image display region with a relatively high rewrite frequency. By this, the same effect as that obtained when a counter voltage is switched according to the rewrite frequency can be obtained. Thus, flicker occurring in each region of the display screen can be suppressed.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: February 28, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiji Kaneko, Kaoru Yamamoto, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20170038651
    Abstract: A TFT substrate (100A) of a liquid crystal display panel includes: an organic interlayer insulating layer (24) covering a TFT; a first transparent electrically-conductive layer (25) provided in the first region of a surface of the organic interlayer insulating layer (24); and an inorganic dielectric layer (26) covering the first transparent electrically-conductive layer (25) and provided in a second region of the surface of the organic interlayer insulating layer (24) which is different from the first region, the inorganic dielectric layer (26) containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer (24) is not less than 3.45 nm and not more than 5.20 nm.
    Type: Application
    Filed: April 9, 2015
    Publication date: February 9, 2017
    Inventors: Yutaka TAKAMARU, Seiji KANEKO, Takao SAITOH, Yohsuke KANZAKI, Keisuke IDE, Hiroshi MATSUKIZONO
  • Patent number: 9520097
    Abstract: In a display control circuit (200) of a display device, an image pattern detection portion (230) detects whether an image is an anti-flicker pattern or not, and when it is an anti-flicker pattern, a backlight source is driven (typically, such that its luminance changes in the opposite phase relative to luminance changes that would occur), on the basis of predicted values, which are predetermined so as to compensate for the luminance changes that would occur. Moreover, the backlight is not turned on during the scanning period. As a result, flicker due to current leakage, etc., can be reduced or eliminated in a display device for which a scanning period and a scan stop period are set.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 13, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takamaru, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Noriaki Yamaguchi, Shigeyasu Mori
  • Publication number: 20160349556
    Abstract: A semiconductor device (100A) includes a substrate (11); a TFT (10A) supported on the substrate, the TFT including an oxide semiconductor layer (16); an organic insulating layer (24) covering the TFT; a lower layer electrode (32) on the organic insulating layer; a dielectric layer (34) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode (36) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×1021 atoms/cm3 or less.
    Type: Application
    Filed: February 2, 2015
    Publication date: December 1, 2016
    Inventors: Yohsuke KANZAKI, Seiji KANEKO, Takao SAITOH, Yutaka TAKAMARU, Keisuke IDE
  • Patent number: 9507225
    Abstract: The present invention includes: switching elements (5) in respective sub-pixels (P); an interlayer insulating film covering the switching elements (5); a first transparent electrode (18a) on the interlayer insulating film, the first transparent electrode (18a) having openings (18c) for each sub-pixel (P); an inorganic insulating film covering the first transparent electrode (18a); and a plurality of second transparent electrodes (20a) on the inorganic insulating film, each of the second transparent electrodes (20a) being connected to one of the switching elements (5) through the respective openings (18c) in the first transparent electrode (18a). The respective second transparent electrodes (20a) have a line-and-space pattern (F) constituted of line-shaped line parts (L) and spaces (S), the spaces (S) not overlapping the respective openings (18c) in the first transparent electrode (18a).
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: November 29, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Nakazawa, Seiji Kaneko
  • Patent number: 9341904
    Abstract: The TFT substrate (10) of this liquid crystal display device (100) includes: a TFT (11) which is provided for each pixel; an upper electrode (12) which is electrically connected to the TFT's drain electrode (11d); a lower electrode (13) which is arranged under the upper electrode; and a dielectric layer (14) which is arranged between the upper and lower electrodes. Its counter substrate (20) includes a counter electrode (21) which faces the upper electrode. The upper electrode has first and second regions (R1, R2) which have mutually different electrode structures, and a third region (R3) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion (12c) that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L1) that splits each pixel into two adjacent regions in a row direction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Yutaka Takamaru, Kohhei Tanaka, Mitsuhiro Murata, Akira Shibazaki, Ken Kuboki
  • Patent number: 9336736
    Abstract: Provided is a liquid crystal display device with reduced power consumption employing a CS drive method. A CS driver (500) consists of a CS shift register (510) and a CS output portion (520). The CS shift register (510) outputs control signals (COUT(1) to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion (520) outputs auxiliary capacitance signals (CSS(1) to CSS(m)) in accordance with the control signals (COUT(1) to COUT(m)), respectively. An idle period (T2) is set following a scanning period (T1). During the idle period (T2), the CS driver (500) is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck2). The idle-period CS frequency (fcck2) is lower than a scanning-period CS frequency (fcck1).
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: May 10, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Seiji Kaneko, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Patent number: 9310911
    Abstract: A semiconductor layer for an active element included in each of a plurality of pixels in a display section is constituted by an oxide layer containing at least one element selected from the group consisting of In, Ga, and Zn. There is provided, for the display section, a liquid crystal panel's timing controller (13) configured to carry out control so that (i) a length of a first period during which image data is written is not more than twice that of the second period and/or (ii) one (1) frame period is longer than 16.7 msec.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 12, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuhiro Sugita, Kazutoshi Kida, Shinji Yamagishi, Yuhji Yashiro, Hiroyuki Ogawa, Shigeyasu Mori, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru
  • Patent number: 9261746
    Abstract: In order to suppress crosstalk between a pixel electrode and a source line to reduce flicker, an LCD device includes: gate lines 102 and source lines 105 which are provided in a grid pattern; pixel electrodes 111 arranged in a matrix pattern so as to correspond to intersections of the gate lines and the source lines; a transparent auxiliary capacitor electrode 109; and switching elements 121 configured to apply an image signal voltage supplied from the source line 105 to the pixel electrode 111 according to a scanning signal applied from the gate line 102. The switching element 121 is formed by using an oxide semiconductor layer 104, and the transparent auxiliary capacitor electrode 109 is provided between the source line 105 and the pixel electrode 111.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 16, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20150049290
    Abstract: The TFT substrate (10) of this liquid crystal display device (100) includes: a TFT (11) which is provided for each pixel; an upper electrode (12) which is electrically connected to the TFT's drain electrode (11d); a lower electrode (13) which is arranged under the upper electrode; and a dielectric layer (14) which is arranged between the upper and lower electrodes. Its counter substrate (20) includes a counter electrode (21) which faces the upper electrode. The upper electrode has first and second regions (R1, R2) which have mutually different electrode structures, and a third region (R3) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion (12c) that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L1) that splits each pixel into two adjacent regions in a row direction.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 19, 2015
    Inventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Yutaka Takamaru, Kohhei Tanaka, Mitsuhiro Murata, Akira Shibazaki, Ken Kuboki
  • Publication number: 20150049071
    Abstract: Provided are: a liquid crystal display device capable of rapidly discharging an image signal which is held in a pixel formation portion, when a power supply thereof is turned off; and a driving method of the liquid crystal display device. If the liquid crystal display device shifts to an off-sequence mode, then a data signal Vd with a potential Vdoff1 corresponding to a shift amount ?V3 lowered by a coupling effect of a parasitic capacitance formed between a gate terminal and drain terminal of a thin film transistor (12) is applied to a signal line SL. When a scanning signal Vg turns to a high level, the data signal Vd applied to the signal line SL is written into the pixel formation portion (11), and a potential of a pixel signal Vpix becomes the Vdoff1. When the scanning signal Vg falls to a ground potential GND after an elapse of a period t1, the potential of the pixel signal Vpix is lowered by a shift amount ?V3, and accordingly, the potential of the pixel signal Vpix becomes the ground potential GND.
    Type: Application
    Filed: April 5, 2013
    Publication date: February 19, 2015
    Inventor: Seiji Kaneko
  • Publication number: 20140320479
    Abstract: At the time of partial drive, the levels of voltages applied to data lines SL1 to SLn are switched according to a rewrite frequency set for each region of a display screen. For example, in a still-image display region with a relatively low rewrite frequency, the levels of the voltages applied to the data lines SL1 to SLn are set to be higher than those for a moving-image display region with a relatively high rewrite frequency. By this, the same effect as that obtained when a counter voltage is switched according to the rewrite frequency can be obtained. Thus, flicker occurring in each region of the display screen can be suppressed.
    Type: Application
    Filed: September 20, 2012
    Publication date: October 30, 2014
    Inventors: Seiji Kaneko, Kaoru Yamamoto, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20140307195
    Abstract: The present invention includes: switching elements (5) in respective sub-pixels (P); an interlayer insulating film covering the switching elements (5); a first transparent electrode (18a) on the interlayer insulating film, the first transparent electrode (18a) having openings (18c) for each sub-pixel (P); an inorganic insulating film covering the first transparent electrode (18a); and a plurality of second transparent electrodes (20a) on the inorganic insulating film, each of the second transparent electrodes (20a) being connected to one of the switching elements (5) through the respective openings (18c) in the first transparent electrode (18a). The respective second transparent electrodes (20a) have a line-and-space pattern (F) constituted of line-shaped line parts (L) and spaces (S), the spaces (S) not overlapping the respective openings (18c) in the first transparent electrode (18a).
    Type: Application
    Filed: November 9, 2012
    Publication date: October 16, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Nakazawa, Seiji Kaneko
  • Publication number: 20140267464
    Abstract: In a display control circuit (200) of a display device, an image pattern detection portion (230) detects whether an image is an anti-flicker pattern or not, and when it is an anti-flicker pattern, a backlight source is driven (typically, such that its luminance changes in the opposite phase relative to luminance changes that would occur), on the basis of predicted values, which are predetermined so as to compensate for the luminance changes that would occur. Moreover, the backlight is not turned on during the scanning period. As a result, flicker due to current leakage, etc., can be reduced or eliminated in a display device for which a scanning period and a scan stop period are set.
    Type: Application
    Filed: October 31, 2012
    Publication date: September 18, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takamaru, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Noriaki Yamaguchi, Shigeyasu Mori
  • Publication number: 20140176845
    Abstract: In order to suppress crosstalk between a pixel electrode and a source line to reduce flicker, an LCD device includes: gate lines 102 and source lines 105 which are provided in a grid pattern; pixel electrodes 111 arranged in a matrix pattern so as to correspond to intersections of the gate lines and the source lines; a transparent auxiliary capacitor electrode 109; and switching elements 121 configured to apply an image signal voltage supplied from the source line 105 to the pixel electrode 111 according to a scanning signal applied from the gate line 102. The switching element 121 is formed by using an oxide semiconductor layer 104, and the transparent auxiliary capacitor electrode 109 is provided between the source line 105 and the pixel electrode 111.
    Type: Application
    Filed: August 3, 2012
    Publication date: June 26, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Yutaka Takamaru, Shigeyasu Mori