Patents by Inventor Sen Huang

Sen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180166434
    Abstract: A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along X-direction between 2 ?m to 5 ?m and a second length along Y-direction between 3 ?m to 5 ?m.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 14, 2018
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20180166441
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Application
    Filed: November 28, 2017
    Publication date: June 14, 2018
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9985020
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yi-Kuan Wu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9985123
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Patent number: 9984974
    Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Publication number: 20180142118
    Abstract: A low-VOC-emission waterborne coating is prepared from a waterborne acrylic emulsion, a hydrophilic cross-linking agent, a coalescing agent, additives and a pigment, and the waterborne acrylic emulsion is formed from performing emulsion polymerization on those reactive monomers including an alkyl-group-containing methyl acrylate, a hydroxyl-group-containing methyl acrylate, a carboxyl-group-containing methacrylic acid, a hydroxyl-group-containing acrylic polyester (polyether) polyol, and a methyl acrylate containing alkene-based unsaturated functional groups, which features high hardness, good adhesion, high luster, high acid resistance, high alkali resistance, good weatherability, high solvent resistance, high scrap resistance and high thermal shock resistance.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 24, 2018
    Inventors: Te-Chao LIAO, Sen-Huang HSU, Hung-Hsun WU, Hui-Chun CHUANG
  • Publication number: 20180139321
    Abstract: A remotely managing and controlling system and a remotely managing and controlling method are provided to a user fbr receiving feedback information and control right of the target device through a remote connecting device. To achieve the above goal, a remote control program is proposed and installed in a controlling device, named controlling terminal, and the target device, to determine whether operation des can be executed through the remote connecting device. The remote connecting device transmits control co mmands and data to the target device, and receives the feedback information and the control right of the target device. Then, the controlling terminal can control the target device according to the feedback information for increasing the efficiency of data management. Further, the system and the method can receive a location of the target device through a tracing platform, and control the target device for increasing security of data stored in the target device.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Jian-Jr Lin, Ke-Sen Huang
  • Publication number: 20180137723
    Abstract: An intercom system for emergency rescue has a user extension, an administration server and a management device. The user extension has a serial number and is capable of generating an alarm signal by operation. The administration server connects to the user extension and the management device to receive the alarm signal. A plot plan recording a location of the user extension is stored in the administration server. The administration server transmits the plot plan with the location of the user extension that outputs the alarm signal to the management device to display. Therefore, an administrator equipped with the management device communicates with the user extension via a video connection established by the administration server. With the help of the plot plan and the video connection, the administrator provides timely assistance to reduce casualties.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 17, 2018
    Inventors: JIAN-JR LIN, KE-SEN HUANG
  • Publication number: 20180130742
    Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9943103
    Abstract: The present invention provides for a grasping device intended for use by golfers to hold a cigar above the ground. The device is constructed from a length of wire formed as two halves of a golfing tool. The two halves are intertwined into opposing halves, forming an actuator that may be squeezed to open a cigar grasper. An end is suited for use to repair ball marks and divots on a golf course.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 17, 2018
    Assignee: Cigar Companion Concepts, LLC
    Inventors: Stephen Marconi, Fou Sen Huang
  • Publication number: 20180101767
    Abstract: Techniques for iterative query-based analysis of text are described. According to various implementations, a neural network architecture is implemented receives a query for information about text content, and iteratively analyzes the content using the query. During the analysis a state of the query evolves until it reaches a termination state, at which point the state of the query is output as an answer to the initial query.
    Type: Application
    Filed: June 30, 2017
    Publication date: April 12, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Po-Sen Huang, Jianfeng Gao, Weizhu Chen, Yelong Shen
  • Patent number: 9941215
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Patent number: 9932452
    Abstract: A release film is provided for supporting an ultrathin ceramic green sheet having a thickness of 0.5 to 1.0 ?m, and the release film due to containing modified organic particles and an antistatic agent has a slippery releasing surface with a low friction coefficient and hence excellent coatability and releasing properties; resulted in that when the release film is rolled up, the rolled surfaces do not adhere to each other, and when the ultrathin ceramic green sheet is peeled off from the release film, the ultrathin ceramic green sheet due to a relatively small electrostatic force being generated is without breaking; so that the release film contributes to increasing the yield of ultrathin ceramic green sheet.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 3, 2018
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Sen-Huang Hsu, Chao-Quan Wu
  • Patent number: 9929134
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20180068951
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
    Type: Application
    Filed: October 4, 2016
    Publication date: March 8, 2018
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Publication number: 20180058936
    Abstract: A far infrared sensor package includes a package body and a plurality of far infrared sensor array integrated circuits. The plurality of far infrared sensor array integrated circuits are disposed on a same plane and inside the package body. Each of the far infrared sensor array integrated circuits includes a far infrared sensing element array of a same size.
    Type: Application
    Filed: December 30, 2016
    Publication date: March 1, 2018
    Inventors: Chih-Ming Sun, Sen-Huang Huang
  • Patent number: 9899322
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Publication number: 20180040558
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
    Type: Application
    Filed: August 26, 2016
    Publication date: February 8, 2018
    Inventors: Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9875941
    Abstract: A method for fabricating semiconductor device is disclosed. First, a first fin-shaped structure and a second fin-shaped structure are formed on a substrate, and a shallow trench isolation (STI) is formed around the first fin-shaped structure and the second fin-shaped structure, a patterned hard mask is formed on the STI. Next, part of the first fin-shaped structure and part of the second fin-shaped structure adjacent to two sides of the patterned hard mask are removed for forming a first recess and a second recess, and a dielectric material is formed into the first recess and the second recess.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 9870996
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang