Abstract: According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.

Abstract: A method of operating a storage device that is connected to a host includes entering an authentication mode; and performing the authentication operation responsive to entering the authentication mode. The performing of the authentication operation includes receiving a read command and a first random authentication address from the host; performing an authentication procedure based on at least a portion of the first random authentication address; and generating result data responsive to performing the authentication algorithm.

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

Abstract: Disclosed herein is an ultrasound imaging apparatus capable of setting a region of interest having a shape corresponding to a shape of the cervix canal in an elasticity image of the cervix and displaying the region of interest, and a control method thereof. The ultrasound imaging apparatus includes a display unit configured to display an ultrasound elasticity image and a controller configured to select a point included in a path corresponding to the cervix canal in the elasticity image of the cervix displayed on the display unit, configured to set a region of interest having a shape corresponding to a shape of at least one portion of the cervix canal based on the selected point, and configured to display the region of interest on the display unit.

Abstract: A method of controlling a first memory controller that controls a non-volatile memory device includes: the first memory controller receiving first data and a first physical address from a second memory controller via a first interface of the first memory controller; the first memory controller storing the first data in a non-volatile memory buffer of the first memory controller; and the first memory controller programming the first data stored in the non-volatile memory buffer in a first physical region of the non-volatile memory device corresponding to the first physical address.

Abstract: A device performing a power gating operation includes a switch control signal generation circuit and a power gating circuit. The switch control signal generation circuit controls an operation that generates a first switch control signal and a second switch control signal from a mode signal based on a comparison result of a first power source voltage and a second power source voltage until a mode register set operation is performed after a power-up period ends. The power gating circuit drives a power source voltage to the first power source voltage or the second power source voltage based on the first switch control signal and the second switch control signal.

Abstract: A device and method for recognizing an object included in an input image are provided, the device for recognizing the object included in the input image includes a memory in which at least one program is stored; a camera configured to capture an environment around the device; and at least one processor configured to execute the at least one program to recognize an object included in an input image, wherein the at least one program includes instructions to: obtain the input image by controlling the camera; obtain information about the environment around the device that obtains the input image; determine, based on the information about the environment, a standard for using a plurality of feature value sets in a combined way, the plurality of feature value sets being used to recognize the object in the input image; and recognize the object included in the input image, by using the plurality of feature value sets based on the determined standard for using the plurality of feature value sets in the combined way.

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

Abstract: A pulse rate and respiratory rate measuring method includes acquiring a facial image comprising a face of a user, calculating a color signal from a predetermined number of skin regions of interest in the face of the user in the facial image, calculating a pulse wave signal or a respiratory signal by converting an extracted signal into a time domain after extracting a signal in a frequency band corresponding to pulse or respiration in frequency data obtained by converting the color signal into a frequency domain, and measuring a pulse rate or a respiratory rate corresponding to the frequency band based on peak interval information in the pulse wave signal or the respiratory signal.

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: There is provided an ammonia gas removal system, including a fine bubble generation device which is configured to receive at least a portion of scrubber process water from a storage tank, and to generate fine bubbles containing carbon dioxide gas in the received scrubber process water, the storage tank being configured to store the scrubber process water to be provided to a gas scrubber, the gas scrubber being configured to spray the process water onto ammonia-containing gas.

Abstract: An electronic device is disclosed. An electronic device comprises: a first memory in which an operating system and an application program executed on the operating system are stored; a second memory; a processor for loading at least some codes among codes corresponding to an application program from the first memory to the second memory, and when access information of the codes loaded in the second memory is received from a kernel of an operating system, accessing an area in which the loaded codes are stored, on the basis of the received information and executing the application program; and a snoop for monitoring access to an area in which a preset code, the access of which has been limited, from among codes loaded in the second memory is stored.

Abstract: The present invention provides a method for preparing a PNA oligomer. More specifically, the present invention can prepare a PNA oligomer which is easily separable from byproducts through a simple and short process by using PNA dimers, PNA trimers or PNA tetramers, and which has extremely high yields and purity.

Abstract: A method for charging a battery includes: determining a first charging section, in which a current charging rate of the battery is located, from among a plurality of charging sections predetermined based on a functional relation between a state of charge of the battery and an open circuit voltage of an anode of the battery; and charging the battery for the first charging section with a first charging rate corresponding to the first charging section.

Abstract: A blood pressure measurement method, includes: receiving an image comprising a skin image of a user; converting each color data of skin regions of interest in a predetermined part of the skin image into frequency domain data; calculating a maximum peak value of pulses in pulse related frequency domain data of the frequency domain data, a maximum frequency value corresponding to the maximum peak value, and a maximum peak frequency phase difference of a phase difference of the maximum frequency value between the skin regions; calculating a pulse transit time as a function of the maximum frequency value and the maximum peak frequency phase difference; and calculating a blood pressure of the user as a function of the maximum peak value, the maximum frequency value, and the pulse transit time.