Abstract: With regard to a function group including all or some functions included in one of multiple binary codes stored in the memory device, a binary code including a first function that is executed at a first timepoint is loaded into a first memory area at a second timepoint that precedes the first time point, thereby minimizing the operation delay time of the memory system, and minimizing the overhead occurring in the processing of calling a specific function.

Abstract: A secondary battery includes an electrode assembly having a positive electrode provided with a positive electrode tab, a separator, and a negative electrode provided with a negative electrode tab, the positive electrode, the separator, and the negative electrode being wound, the electrode assembly having a core part at a center thereof; a can configured to receive the electrode assembly therein, the negative electrode tab being connected to the can; a cap assembly coupled to an opening of the can, the positive electrode tab being connected to the cap assembly; and a reinforcing member provided on an end of the separator exposed beyond the positive electrode or the negative electrode to prevent heat of the positive electrode tab or the negative electrode tab from being transferred to the separator.

Abstract: A display device includes a substrate, a first active pattern, a first gate electrode, a second active pattern, a second gate electrode, a first connecting pattern, and a second connecting pattern. The first connecting pattern is disposed on the second active pattern and is electrically connected to the first gate electrode, and the second connecting pattern is disposed on the first connecting pattern and is electrically connected to the first connecting pattern and the second active pattern.

Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.

Abstract: An encryption key management method includes: receiving a data registration request from a supplier terminal, determining a data identifier associated with the content data, encrypting a master key with a public key of the supplier terminal, and providing the supplier terminal with the master key encrypted with the public key of the supplier terminal, the data identifier, and a key update count value; receiving a subscription application related to the data identifier from a first subscriber terminal, encrypting the master key with a public key of the first subscriber terminal, and providing the first subscriber terminal with the master key encrypted with the public key of the first subscriber terminal and the key update count value; receiving encrypted content data encrypted with the symmetric key and a hash for the content data from the supplier terminal; and transmitting the encrypted content data and the hash to the first subscriber terminal.

Abstract: The present invention relates to a novel heterocyclic compound usable in an organic light-emitting device and to an organic light-emitting device comprising same, wherein [chemical formula A] is as described in the detailed description of the invention.

Abstract: A steroid sulfatase inhibitor provided by the present invention is a safe substance without toxicity and adverse effects, has inhibitory activity against various viruses, and thus is capable of effectively preventing, ameliorating, or treating viral infections or diseases caused by viral infections.

Abstract: Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number of bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.

Abstract: A memory includes a memory device including plural memory blocks, each memory block including plural pages, and a controller coupled to the memory device and configured to select a target memory block among the plural memory blocks, the target memory block including a first page to an N page (N is a positive integer), and program data in the target memory block, based on a type of the data, either in a first direction from the first page to the N page or in a second direction from the N page to the first page.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory device controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: There are provided a memory controller for managing meta data and an operating method of the memory controller. The memory controller includes: a buffer memory for storing meta data used to control an operation of a memory device; and a central processing unit for updating the meta data stored in the buffer memory whenever the operation of the memory device is controlled. The central processing unit may transmit the meta data stored in the buffer memory to a host at a first frequency, and transmit the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency.

Abstract: An electronic device includes a memory controller selecting map data to be output to a host. The memory controller includes an address counter and a map data selector. The address counter counts a number of times a logical block address corresponding to a request is received based on the request received from the host and outputs an activation signal indicating that an index to which the logical block address belongs is an activation index when an activation count corresponding to the index is equal to or greater than a preset value, the activation count being generated based on a counting result. The map data selector selects map data to be output to the host based on the activation signal. The address counter decreases the activation count by a preset size when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data.

Abstract: Provided herein is a memory controller and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks may include a workload determiner and a write controller. The workload determiner is configured to set a threshold number of free blocks for determining whether a number of free blocks, among the plurality of memory blocks, falls within a normal range based on a predicted idle period of the memory device, and to determine a workload pattern of the memory device by comparing the number of free blocks with the threshold number of free blocks. The write controller is configured to control the memory device so that one of a fast write operation and a normal write operation is selectively performed depending on the workload pattern.

Abstract: A data storage device may include: a nonvolatile memory configured to store L2P (Logical to Physical) map data and user data; and a controller configured to determine whether read commands which are sequentially transferred from a host device correspond to a backward sequential read, increase a backward sequential read count when the read commands are backward sequential read, set a pre-read start logical block address (LBA) and a length according to a preset condition, when the backward sequential read count is equal to or greater than a reference value, and load an L2P map of the corresponding LBA and user data corresponding to the L2P map from the nonvolatile memory in advance.

Abstract: A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory groups, each of which includes a plurality of memory regions in interleaving units and a controller configured to determine and manage interleaving-aware dirty (IAD) of a write-requested logical address whenever write-requested data is written in the nonvolatile memory device, and select a victim memory group among the plurality of memory groups using the interleaving-aware dirty.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device may include: generating pre-read information based on a first read request, reading out 1st sub-chunks respectively included in a plurality of data chunks from the nonvolatile memory device, and providing a host with the read 1st sub-chunks, wherein the first read request includes respective addresses of the 1st sub-chunks; starting, after the 1st sub-chunks are provided to the host, a pre-read operation of reading out 2nd sub-chunks respectively included in the plurality of data chunks from the nonvolatile memory device based on the pre-read information and storing the read 2nd sub-chunks into a memory in the controller; and providing, after the pre-read operation is started, the host with the 2nd sub-chunks stored in the memory in response to a second read request received from the host.