Abstract: A wafer cleaning equipment includes a housing to be positioned adjacent to a wafer, a hollow region in the housing, a laser module that outputs a laser beam having a profile of the laser beam includes a first region having a first intensity and a second region having a second intensity greater than the first intensity, the laser beam being output into the hollow region, and a transparent window that covers an upper part of the hollow region and transmits the laser beam to be incident on an entirety of a lower surface of the wafer.

Abstract: A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.

Abstract: A display device includes a first active pattern, a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction, a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction, a second active pattern disposed on the second conductive pattern and including a material different from a material of the first active pattern, and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping the third gate line and connected to the third gate line, and a second upper electrode overlapping the fourth gate line and connected to the fourth gate line.

Abstract: A display device includes a substrate, a first active pattern, a first gate electrode, a second active pattern, a second gate electrode, a first connecting pattern, and a second connecting pattern. The first connecting pattern is disposed on the second active pattern and is electrically connected to the first gate electrode, and the second connecting pattern is disposed on the first connecting pattern and is electrically connected to the first connecting pattern and the second active pattern.

Abstract: The present disclosure provides a thermoplastic resin composition having high rigidity and a low coefficient of linear thermal expansion and a molded article including the same. The thermoplastic resin composition includes a first propylene-ethylene copolymer, a second propylene-ethylene copolymer, a thermoplastic elastomer, an inorganic filler, and a sodium-phosphate-based nucleating agent as appropriate, and thus a molded article produced therefrom can exhibit improved mechanical rigidity, impact resistance, and dimensional stability. Even when formed to a low thickness for weight reduction, the molded article can be imparted with excellent processability, high tensile strength, a high flexural modulus, and high impact strength.

Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.

Abstract: A memory includes a memory device including plural memory blocks, each memory block including plural pages, and a controller coupled to the memory device and configured to select a target memory block among the plural memory blocks, the target memory block including a first page to an N page (N is a positive integer), and program data in the target memory block, based on a type of the data, either in a first direction from the first page to the N page or in a second direction from the N page to the first page.

Abstract: An antenna structure according to an embodiment of the present disclosure includes a dielectric layer, and a plurality of antenna units arranged on a top surface of the dielectric layer. Each of the plurality of antenna units includes a radiator, a transmission line including a first transmission line and a second transmission line that extend in different directions to be connected to the radiator, an upper parasitic element adjacent to an upper portion of the radiator, and a lower parasitic element adjacent to a lower portion of the radiator and the transmission line. Feeding signals of different phases are applied to the first transmission line and the second transmission line.

Abstract: An antenna structure according to an embodiment of the present disclosure includes a dielectric layer and a plurality of antenna units arranged on a top surface of the dielectric layer. Each of the plurality of antenna units includes a radiator, a first transmission line and a second transmission line extending in different directions to be connected to the radiator, an upper parasitic element adjacent to an upper portion of the radiator, and a lower parasitic element adjacent to a lower portion of the radiator.

Abstract: An antenna structure according to an embodiment of the present disclosure includes an antenna unit array including a plurality of antenna units, and a parasitic element disposed to be adjacent to the antenna units and to be electrically and physically separated from the antenna units. Each of the antenna units includes a radiator, and a transmission line including a first transmission line and a second transmission line connected to the radiator in different directions. The parasitic element includes a first parasitic element disposed between the first transmission line and the second transmission line included in the same antenna unit, and a second parasitic element disposed between the first transmission line and the second transmission line included in different neighboring antenna units. The second parasitic element includes a branched portion including a first branched portion and a second branched portion bent in different directions.

Abstract: An antenna structure according to an embodiment of the present disclosure includes a dielectric layer, and an antenna unit disposed on a top surface of the dielectric layer. The antenna unit includes a radiator including convex portions and concave portions, a transmission line including a first transmission line and a second transmission line that extend in different directions to be connected to the radiator, and a parasitic element disposed to be adjacent to the transmission line and electrically and physically separated from the transmission line and the radiator. A length of the parasitic element in an extension direction of the transmission line is from 45% to 70% of a half wavelength (?/2) at a maximum resonance frequency from the antenna unit.

Abstract: A display device includes a polycrystalline semiconductor including a channel and electrodes of a driving transistor; a gate electrode of the driving transistor on the channel of the driving transistor; a first storage electrode on the gate electrode of the driving transistor; a light blocking layer of a first transistor and a light blocking layer of a second transistor; an oxide semiconductor including a channel and electrodes of the first transistor, and a channel and electrodes of the second transistor; a gate electrode of the first transistor on the channel of the first transistor; and a gate electrode of the second transistor on the channel of the second transistor. The light blocking layer of the first transistor and the first storage electrode are on a same layer, and the light blocking layer of the second transistor and the gate electrode of the driving transistor are on a same layer.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory device controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: A focus scan type imaging device for imaging a target object in a sample that induces aberration proposed. The device includes: a light source unit for emitting a beam; an optical interferometer for splitting the beam emitted from the light source into a sample wave and a reference wave, and providing an interference wave formed by interference between a reflection wave that is the sample wave reflected from the sample and the reference wave; a camera module for imaging the interference wave; a scanning mirror disposed on an optical path of the sample wave of the optical interferometer and configured to reflect the sample wave to cause the sample wave to scan the sample; a wavefront shaping modulator disposed on the optical path of the sample wave of the optical interferometer; and an imaging controller configured to operate in a phase map calculation mode and in an imaging mode.

Abstract: A hierarchical fault classification method for a fuel cell system, a multi-stage fault diagnosis method therefor, and a fault diagnosis device therefor are disclosed. The fuel cell system is divided into a subsystem, a component, and an element step by step. The multi-stage fault diagnosis method includes detecting a subsystem, a fault of which occurs, in the fuel cell system composed of a plurality of subsystems and detecting an upper-level component, which causes the fault, among upper-level components included in the subsystem, the fault of which occurs, using measurement data and a control signal.

Abstract: Disclosed is a universal jig for charging and discharging a secondary battery cell. The universal jig includes a cell zig assembly including: a cell receiving part for receiving the secondary battery cell thereon; and a zig for a positive electrode terminal and a zig for a negative electrode terminal disposed above the cell receiving part and in contact with a positive electrode terminal and a negative electrode terminal of the secondary battery cell to apply current thereto, respectively; and a zig rotation inducing assembly connected, via a rotation center shaft thereof, to one face or an opposite face of the cell zig assembly on which the zig for the positive electrode terminal and the zig for the negative electrode terminal are disposed, wherein the zig rotation inducing assembly allows the cell zig assembly to rotate around the rotation center shaft.

Abstract: A wet etching apparatus includes a process bath having an internal space configured to receive an etchant and having a support unit, on which a wafer is disposed to be in contact with the etchant. A laser unit is disposed above the process bath and is configured to direct a laser beam to the wafer and to heat the wafer thereby. An etchant supply unit is configured to supply the etchant to the internal space of the process bath.

Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: Provided herein is a memory controller and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks may include a workload determiner and a write controller. The workload determiner is configured to set a threshold number of free blocks for determining whether a number of free blocks, among the plurality of memory blocks, falls within a normal range based on a predicted idle period of the memory device, and to determine a workload pattern of the memory device by comparing the number of free blocks with the threshold number of free blocks. The write controller is configured to control the memory device so that one of a fast write operation and a normal write operation is selectively performed depending on the workload pattern.