Abstract: A method to map a plurality of feature maps of a neural network onto a memory hierarchy includes mapping a first feature map of the plurality of feature maps to a memory in a memory hierarchy having available memory space and providing quickest access to the first feature map. The method also includes, when the first feature map expires, removing the first feature map from the memory used to store the first feature map.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: A method of implementing memory transfers for image warping in an electronic device is described. The method comprises receiving an input tile associated with an image; generating a geometric boundary around pixels of the input tile; and remapping the pixels in the geometric boundary to an output tile. An electronic device and a non-transitory computer readable storage medium for performing the method are also disclosed.

Abstract: A wearable device is provided for authentication that includes a memory element and processing circuitry coupled to the memory element. The memory element configured to store a plurality of user profiles. The processing circuitry is configured to identify a pairing between the wearable device and a device. The processing circuitry is configured to identify a user of the wearable device. The processing circuitry also is configured to determine if the identified user matches a profile of the plurality of user profiles. The processing circuitry is also configured to responsive to the identified user matching the profile, determine if the profile provides authorization to access the device. The processing circuitry is also configured to responsive to the profile providing authorization to the device, send a message to the device authorizing access to the device.

Abstract: Provided is a method for generating a one class model based on a data frequency. The method for generating a one class model based on a data frequency includes: generating, by a machine learning apparatus, a plurality of spatial coordinates by arranging a plurality of learning data in corresponding coordinates in a feature space; classifying, by the machine learning apparatus, the plurality of spatial coordinates into a plurality of internal coordinates PI and a plurality of external coordinates PO based on a frequency of the learning data arranged in the respective spatial coordinates which belong to the plurality of spatial coordinates; and generating, by the machine learning apparatus, a one class model based on the plurality of internal coordinates PI based on mutual spatial distances of the plurality of external coordinates PO and the plurality of internal coordinates PI.

Abstract: An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit is coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor is configured to execute instruction words received on the system bus and has a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract: Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.

Abstract: Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A wearable device is provided for authentication that includes a memory element and processing circuitry coupled to the memory element. The memory element configured to store a plurality of user profiles. The processing circuitry is configured to identify a pairing between the wearable device and a device. The processing circuitry is configured to identify a user of the wearable device. The processing circuitry also is configured to determine if the identified user matches a profile of the plurality of user profiles. The processing circuitry is also configured to responsive to the identified user matching the profile, determine if the profile provides authorization to access the device. The processing circuitry is also configured to responsive to the profile providing authorization to the device, send a message to the device authorizing access to the device.

Abstract: A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits.

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.