Abstract: In some embodiments, a device includes a multiple-input multiple-output (“MIMO”) decoder module coupled to a first log-likelihood-ratio (“LLR”) computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers. The method further includes performing a K-best breadth-first search on the data to obtain an estimated constellation point. The method further includes providing a user data stream based at least in part on the estimated constellation point.

Abstract: A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.

Abstract: A methods and apparatus for synchronizing a de-interleaver are disclosed. One example method includes fixing a phase of a de-interleaver in a first state; de-interleaving symbols in the signal while the phase of the de-interleaver is in the first state; processing the de-interleaved symbols; detecting if the known information is present in the processed de-interleaved symbols; and switching the phase of the de-interleaver between the first state and a second state when the known information is detected in the processed de-interleaved symbols.

Abstract: A Viterbi decoder includes a branch metric unit for generating branch metrics between two states at two different time periods, a traceback unit, a traceback memory and an add-compare-select circuit. The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a plurality of branch metrics from the branch metric unit and a plurality of pre-calculated path metrics, where at least one of the add-compare-select sub-circuits receives a set of pre-calculated path metrics from another one of the add-compare-select sub-circuits.

Abstract: A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.

Abstract: A high speed add-compare-select (ACS) circuit for a radix-4 Viterbi decoder has a lower critical path delay than that achievable using a traditional ACS circuit suitable for use with a radix-4 Viterbi decoder. The high speed ACS circuit is implemented to achieve a lower critical path delay without increasing the clock rate beyond that required by a radix-2 ACS circuit.

Abstract: A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.

Abstract: A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications.

Abstract: A multiple loop antenna of a radio paging receiver comprising a first loop antenna, and a second loop antenna electrically connected to the first loop antenna, wherein the second loop antenna is positioned with respect to the first loop antenna to receive a radio wave travelling in a direction in which the receiving sensitivity of the first loop antenna is lowered.

Abstract: An extrusion coating apparatus including a body having a liquid dispensing passage for dispensing a coating liquid on a surface of a sheet, the liquid dispensing passage being connected to a manifold formed inside the body, and a hollow core which is disposed in the manifold at a predetermined distance apart from the manifold and includes in the longitudinal direction thereof, a slit through which the coating liquid supplied into the hollow core is uniformly extruded. The apparatus dispenses a coating liquid at a constant pressure to the surface of the sheet through the hollow core, the manifold, and the liquid dispensing passage so that a coating layer having a uniform thickness in the longitudinal and transverse directions thereof is formed on the surface of the sheet. The apparatus can adjust the thickness of the coating layer, and can be easily handled.

Abstract: A semiconductor wafer anchoring device, which includes a platen having a flat upper surface adapted for mounting a semiconductor wafer thereon, an elastic O-ring located between the platen and the semiconductor wafer, and a clamp disposed to face with the O-ring, which is adapted for pressing upon the upper surface of the semiconductor wafer and for anchoring same. The clamp is a ring-type plate having an inner diameter larger than the diameter of the semiconductor wafer, and having a plurality of protrusions projecting from each quadrant of an inner circumferential surface of the ring-type plate toward the center thereof, an end of each protrusion being adapted to be positioned between a chip pattern and the edge of the semiconductor wafer.