Patents by Inventor Seok-Jun Won

Seok-Jun Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7166541
    Abstract: A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: January 23, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Min-Woo Song, Seok-Jun Won, Yong-Kuk Jeong, Dae-Jin Kwon, Weon-Hong Kim
  • Publication number: 20070004133
    Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
    Type: Application
    Filed: September 12, 2006
    Publication date: January 4, 2007
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
  • Publication number: 20060263977
    Abstract: A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
    Type: Application
    Filed: August 3, 2006
    Publication date: November 23, 2006
    Inventors: Wan-don Kim, Jae-hyun Joo, Seok-jun Won, Jung-hee Chung, Jin-yong Kim, Suk-jin Chung
  • Publication number: 20060255463
    Abstract: An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.
    Type: Application
    Filed: July 17, 2006
    Publication date: November 16, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok-Jun Won
  • Patent number: 7125767
    Abstract: In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the upper electrode, and at least one middle dielectric region between the lower dielectric region and the upper dielectric region, the at least one middle dielectric region having a less crystalline region than both the lower dielectric region and the upper dielectric region.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: October 24, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Jung-Hyoung Lee, Seok-Jun Won, Dae-Jin Kwon, Weon-Hong Kim, Min-woo Song
  • Publication number: 20060234466
    Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.
    Type: Application
    Filed: June 14, 2006
    Publication date: October 19, 2006
    Inventors: Yong-Kuk Jeong, Seok-Jun Won, Dae-Jin Kwon, Weon-Hong Kim
  • Publication number: 20060215348
    Abstract: A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
    Type: Application
    Filed: June 1, 2006
    Publication date: September 28, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jun Won, Kang-soo Chu, Weon-Hong Kim
  • Publication number: 20060187611
    Abstract: A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
    Type: Application
    Filed: April 24, 2006
    Publication date: August 24, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jun Won, Kang-soo Chu, Weon-Hong Kim
  • Patent number: 7091548
    Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: August 15, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kuk Jeong, Seok-Jun Won, Dae-Jin Kwon, Weon-Hong Kim
  • Publication number: 20060171098
    Abstract: In a device including multiple metal-insulator-metal (MIM) capacitors and a method of fabricating the same, the multiple MIM capacitors comprise a lower interconnect in a substrate; a first dielectric layer on the lower interconnect; a first intermediate electrode pattern on the first dielectric layer overlapping with the lower interconnect; a second intermediate electrode pattern on the first dielectric layer and spaced apart from the first intermediate electrode pattern in a same plane of the device as the first intermediate electrode pattern; a second dielectric pattern on the second intermediate electrode pattern; and an upper electrode pattern on the second dielectric pattern.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 3, 2006
    Inventor: Seok-Jun Won
  • Patent number: 7084056
    Abstract: An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Jun Won
  • Publication number: 20060163640
    Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corres
    Type: Application
    Filed: January 25, 2006
    Publication date: July 27, 2006
    Inventors: Jung-min Park, Seok-jun Won, Min-woo Song, Yong-kuk Jeong, Dae-jin Kwon, Weon-hong Kim
  • Publication number: 20060156980
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 20, 2006
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Publication number: 20060158829
    Abstract: Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 20, 2006
    Inventors: Dae-jin Kwon, Seok-jun Won, Weon-hong Kim, Yong-kuk Jeong, Min-woo Song, Jung-min Park
  • Publication number: 20060157766
    Abstract: In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first upper electrode pattern on the dielectric layer; an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface; a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern; a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer; and an upper interconnect on the interlayer insulating layer and contacts the second upper electrode.
    Type: Application
    Filed: December 23, 2005
    Publication date: July 20, 2006
    Inventors: Seok-jun Won, Dae-jin Kwon
  • Publication number: 20060124987
    Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.
    Type: Application
    Filed: February 1, 2006
    Publication date: June 15, 2006
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Seok-Jun Won, Myong-geun Yoon, Yong-Kuk Jeong, Dae-jin Kwon
  • Patent number: 7049648
    Abstract: The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: May 23, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Cha-Young Yoo
  • Publication number: 20060105521
    Abstract: Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not exposed, forming an inter-insulating layer by wet-etching the insulating layer so that a region of the lower electrode corresponding to the capacitor forming region is exposed, and sequentially forming a dielectric layer and an upper electrode on the capacitor forming region to fabricate a capacitor.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 18, 2006
    Inventors: Seok-jun Won, Weon-hong Kim, Yong-kuk Jeong
  • Patent number: 7042698
    Abstract: A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Kang-soo Chu, Weon-Hong Kim
  • Patent number: 7042042
    Abstract: Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Cha-young Yoo