Patents by Inventor Seok-Jun Won

Seok-Jun Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040056755
    Abstract: Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred &mgr;&OHgr;·cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.
    Type: Application
    Filed: September 25, 2003
    Publication date: March 25, 2004
    Inventors: Seok-Jun Won, Young-Wook Park
  • Publication number: 20040033661
    Abstract: A semiconductor device and a method for forming the same. A dielectric layer is formed on a semiconductor substrate or on a lower electrode of a capacitor. Vacuum annealing is performed on the dielectric layer. Thus, impurities remaining in the dielectric layer can be effectively removed, and the dielectric layer can be densified. As a result, the electrical characteristics of the semiconductor device are improved. For example, the leakage current characteristics of the dielectric layer are improved and capacitance is increased.
    Type: Application
    Filed: June 2, 2003
    Publication date: February 19, 2004
    Inventors: Jae-Hyun Yeo, Sung-Tae Kim, Young-Sun Kim, In-Sung Park, Seok-Jun Won, Yun-Jung Lee, Ki-Vin Im, Ki-Yeon Park
  • Publication number: 20040033662
    Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 19, 2004
    Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
  • Patent number: 6692795
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: February 17, 2004
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Seok-jun Won, Soon-yeon Park, Cha-young Yoo
  • Patent number: 6680251
    Abstract: A layer is formed by chemical vapor depositing a seeding layer of ruthenium oxide on a substrate at a chemical vapor deposition flow rate ratio of a ruthenium source to oxygen gas. A main layer of ruthenium is chemical vapor deposited on the seeding layer by increasing the chemical vapor deposition flow rate ratio of the ruthenium source to the oxygen gas.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: January 20, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Cha-young Yoo, Sung-tae Kim, Young-wook Park, Yun-jung Lee, Soon-yeon Park
  • Patent number: 6677217
    Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: January 13, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyun Joo, Wan-don Kim, Seok-jun Won, Soon-yeon Park
  • Patent number: 6667209
    Abstract: In a method for forming capacitors of semiconductor devices, a contact plug penetrating an interlayer dielectric (ILD) is formed on a semiconductor substrate. A supporting layer, an etch stop layer, and a molding layer are sequentially formed on the semiconductor substrate where the contact plug is formed. The molding layer is patterned to form a molding pattern. At this time, the molding pattern has an opening exposing an etch stop layer over the contact plug. Next, an adhesive spacer is formed on sidewalls of the opening. The etch stop layer and the supporting layer, which are exposed through the opening where the adhesive spacer is formed, are successively patterned. Thus, the etch stop pattern and the supporting pattern are formed to expose the contact plug. A lower electrode and a sacrificial pattern are formed to sequentially fill a hole region surrounded by sidewalls of the adhesive spacer, the etch stop pattern, and the supporting pattern.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 23, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Yong-Kuk Jeong
  • Patent number: 6653186
    Abstract: Integrated circuit capacitors and methods of fabricating integrated circuit capacitors, according to the present invention, provide an electrically insulating electrode support layer having an opening therein, on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: November 25, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Cha-young Yoo
  • Patent number: 6653155
    Abstract: Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred &mgr;&OHgr;·cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: November 25, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Young-Wook Park
  • Patent number: 6649502
    Abstract: A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: November 18, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cha-young Yoo, Han-jin Lim, Wan-don Kim, Se-jin Lee, Soon-yeon Park, Yong-kuk Jeong, Han-mei Choi, Gyung-hoon Hong, Seok-jun Won
  • Publication number: 20030190808
    Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.
    Type: Application
    Filed: April 30, 2003
    Publication date: October 9, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jin-won Kim, Seok-jun Won, Cha-young Yoo
  • Patent number: 6624069
    Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: September 23, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
  • Patent number: 6613629
    Abstract: Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 2, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Cha-young Yoo, Jae-hyun Joo, Seok-jun Won
  • Publication number: 20030153146
    Abstract: In a method for forming capacitors of semiconductor devices, a contact plug penetrating an interlayer dielectric (ILD) is formed on a semiconductor substrate. A supporting layer, an etch stop layer, and a molding layer are sequentially formed on the semiconductor substrate where the contact plug is formed. The molding layer is patterned to form a molding pattern. At this time, the molding pattern has an opening exposing an etch stop layer over the contact plug. Next, an adhesive spacer is formed on sidewalls of the opening. The etch stop layer and the supporting layer, which are exposed through the opening where the adhesive spacer is formed, are successively patterned. Thus, the etch stop pattern and the supporting pattern are formed to expose the contact plug. A lower electrode and a sacrificial pattern are formed to sequentially fill a hole region surrounded by sidewalls of the adhesive spacer, the etch stop pattern, and the supporting pattern.
    Type: Application
    Filed: January 24, 2003
    Publication date: August 14, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Yong-Kuk Jeong
  • Publication number: 20030124252
    Abstract: A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.
    Type: Application
    Filed: November 6, 2002
    Publication date: July 3, 2003
    Inventors: Soon-Yeon Park, Cha-Young Yoo, Seok-Jun Won
  • Patent number: 6580111
    Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: June 17, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jin-won Kim, Seok-jun Won, Cha-young Yoo
  • Publication number: 20030082869
    Abstract: The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.
    Type: Application
    Filed: December 3, 2002
    Publication date: May 1, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Cha-Young Yoo
  • Patent number: 6537875
    Abstract: The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: March 25, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Cha-Young Yoo
  • Publication number: 20030032238
    Abstract: Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.
    Type: Application
    Filed: August 7, 2002
    Publication date: February 13, 2003
    Inventors: Wan-don Kim, Cha-young Yoo, Jae-hyun Joo, Seok-jun Won
  • Publication number: 20030022521
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.
    Type: Application
    Filed: December 21, 2001
    Publication date: January 30, 2003
    Inventors: Seok-jun Won, Soon-yeon Park, Cha-young Yoo