Patents by Inventor Seok-Woo Nam

Seok-Woo Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410839
    Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
  • Publication number: 20190272979
    Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
  • Publication number: 20180197719
    Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
    Type: Application
    Filed: May 26, 2017
    Publication date: July 12, 2018
    Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
  • Patent number: 9997538
    Abstract: A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked. Separation patterns are disposed to penetrate the stacked structure. A channel structure is disposed between the separation patterns. The channel structure includes a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and includes vertical portions extending from the horizontal portion in a vertical direction and penetrating the stacked structure. A lower structure is interposed between the horizontal portion and the separation patterns. A dielectric structure is interposed between the vertical portions and the stacked structure and extends between the horizontal portion and the stacked structure.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Hoon Son, Yoon Jae Kim, Seok Woo Nam
  • Publication number: 20180130816
    Abstract: A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked. Separation patterns are disposed to penetrate the stacked structure. A channel structure is disposed between the separation patterns. The channel structure includes a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and includes vertical portions extending from the horizontal portion in a vertical direction and penetrating the stacked structure. A lower structure is interposed between the horizontal portion and the separation patterns. A dielectric structure is interposed between the vertical portions and the stacked structure and extends between the horizontal portion and the stacked structure.
    Type: Application
    Filed: May 3, 2017
    Publication date: May 10, 2018
    Inventors: Yong Hoon SON, Yoon Jae KIM, Seok Woo NAM
  • Patent number: 9847422
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Patent number: 9595612
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Publication number: 20170033225
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: JUNG-HWAN KIM, HUN-HYEOUNG LEAM, TAE-HYUN KIM, SEOK-WOO NAM, HYUN NAMKOONG, YONG-SEOK KIM, TEA-KWANG YU
  • Patent number: 9455259
    Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: September 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jin Lim, Youn-Soo Kim, Hyun Park, Soon-Gun Lee, Eun-Ae Cho, Chin-Moo Cho, Sung-Jin Kim, Seok-Woo Nam
  • Patent number: 9449973
    Abstract: A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-jin Lim, Kong-soo Lee, Seok-woo Nam, Dong-chan Kim, Soo-jin Hong
  • Publication number: 20160155838
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Application
    Filed: January 26, 2016
    Publication date: June 2, 2016
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Publication number: 20160079247
    Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.
    Type: Application
    Filed: May 19, 2015
    Publication date: March 17, 2016
    Inventors: Han-Jin Lim, Youn-Soo Kim, Hyun Park, Soon-Gun Lee, Eun-Ae Cho, Chin-Moo Cho, Sung-Jin Kim, Seok-Woo Nam
  • Patent number: 9263588
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Patent number: 9230922
    Abstract: A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): HxSiAy(NR1R2)4-x-y??(1) HxSi(NAR3)4-x??(2) HxSi(R4)z(R5)4-x-z??(3) wherein, independently in the chemical formulas (1), (2), and (3), H is hydrogen, x is 0 to 3, Si is silicon, A is a halogen, y is 1 to 4, N is nitrogen, and R1, R2, R3, and R5 are each independently selected from the group of H, aryl, perhaloaryl, C1-8 alkyl, and C1-8 perhaloalkyl, and R4 is aryl in which at least one hydrogen is replaced with a halogen or C1-8 alkyl in which at least one hydrogen is replaced with a halogen.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han-Jin Lim, Bong-Hyun Kim, Seok-Woo Nam, Dong-Woon Shin, In-Sang Jeon, Soo-Jin Hong
  • Patent number: 9184232
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Patent number: 9153590
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jin Lim, Won-Seok Yoo, Seok-Woo Nam
  • Publication number: 20150179799
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Application
    Filed: March 2, 2015
    Publication date: June 25, 2015
    Inventors: JUNG-HWAN KIM, HUN-HYEOUNG LEAM, TAE-HYUN KIM, SEOK-WOO NAM, HYUN NAMKOONG, YONG-SEOK KIM, TEA-KWANG YU
  • Publication number: 20150137320
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventors: JUNG-HWAN KIM, HUN-HYEOUNG LEAM, TAE-HYUN KIM, SEOK-WOO NAM, HYUN NAMKOONG, YONG-SEOK KIM, TEA-KWANG YU
  • Publication number: 20150124521
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region.
    Type: Application
    Filed: June 5, 2014
    Publication date: May 7, 2015
    Inventors: Han-Jin Lim, Won-Seok Yoo, Seok-Woo Nam
  • Publication number: 20150060862
    Abstract: A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.
    Type: Application
    Filed: April 28, 2014
    Publication date: March 5, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han-jin LIM, Kong-soo LEE, Seok-woo NAM, Dong-chan KIM, Soo-jin HONG