Patents by Inventor Seok-Woo Nam

Seok-Woo Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7741222
    Abstract: An etch stop layer is formed over a first structure by depositing a metal oxide material over the first structure and annealing the deposited metal oxide material. A second structure is formed over the etch stop layer, and a formation is etched through the second structure using the etch stop layer as an etch stop.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: June 22, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Jae-Young Park, Won-Shik Shin, Hyeon-Deok Lee, Ki-Vin Im, Seok-Woo Nam, Hun-Young Lim, Won-Jun Jang, Yong-Woo Hyung
  • Publication number: 20100009508
    Abstract: Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition.
    Type: Application
    Filed: May 15, 2009
    Publication date: January 14, 2010
    Inventors: Han-jin Lim, Jae-young Park, Young-jin Kim, Seok-woo Nam, Bong-hyun Kim, Kyoung-ryul Yoon, Jae-hyoung Chol, Beom-jong Kim
  • Patent number: 7521375
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Publication number: 20080090424
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Publication number: 20080057670
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 6, 2008
    Inventors: Jung Kim, Hun-Hyeoung Leam, Tae-Hyun kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Patent number: 7297620
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7282407
    Abstract: A semiconductor memory device and method of manufacturing a semiconductor memory device that prevents oxidation of the bit lines caused by misalignment which may occur when patterning a storage electrode. An oxidation preventing layer, such as a nitride layer, is formed over the bit lines or in the contact holes to eliminate the diffusion of oxygen into the bit line structure, thereby preventing oxidation of the bit lines.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: October 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-woo Park, Jun-yong Noh, Bon-young Koo, Chang-jin Kang, Chul Jung, Seok-woo Nam
  • Patent number: 7238585
    Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: July 3, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Seok Kim, Ki-Hyun Hwang, Hyo-Jung Kim, Hyeon-Deok Lee, Seok-Woo Nam
  • Publication number: 20070022941
    Abstract: In a method of forming a layer having a lower electrical resistance and a method of manufacturing a semiconductor device, a first layer may be formed on a single crystalline substrate using amorphous silicon doped with impurities. A heat treatment may be performed on the single crystalline substrate at a temperature of about 550° C. to about 600° C. to convert the first layer into a second layer including a single crystalline silicon film transformed from a lower portion of the first layer contacting the single crystalline substrate and a polysilicon film transformed from an upper portion of the first layer. The layer may be formed at a relatively low temperature by a selective epitaxial growth process, and thus degradation or damage to a semiconductor device, which may be generated in a high temperature process, may be reduced.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventors: Jae-Young Park, Young-Jin Kim, Yong-Woo Hyung, Seok-Woo Nam, Kyoung-Seok Kim, Wook-Yeol Yi, Hun-Hyeoung Leam, Kong-Soo Lee, Ko-Eun Lee
  • Publication number: 20070001209
    Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.
    Type: Application
    Filed: September 7, 2006
    Publication date: January 4, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Seok Kim, Ki-Hyun Hwang, Hyo-Jung Kim, Hyeon-Deok Lee, Seok-Woo Nam
  • Patent number: 7153750
    Abstract: A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySi1-xGex layer stacked on the metallic layer. Methods of forming these capacitors also are provided.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ae Chung, Ki-hyun Hwang, Jung-hwan Oh, Hyo-jung Kim, Seok-woo Nam, Won-sik Shin, U-in Chung, Young-sun Kim, Hee-seok Kim, Beom-jun Jin
  • Publication number: 20060267019
    Abstract: In a capacitor having a semiconductor-insulator-metal (SIM) structure, an upper electrode may be formed into a multilayer structure including a polycrystalline semiconductor Group IV material. A dielectric layer may include a metal oxide, and a lower electrode may include a metal-based material. Therefore, a capacitor may have a sufficiently small equivalent oxide thickness (EOT) and/or may have improved current leakage characteristics.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 30, 2006
    Inventors: Kyoung-Seok Kim, Yong-Woo Hyung, Jae-Young Park, Hyeon-Deok Lee, Ki-Vin Im, Wook-Yeol Yi, Ko-Eun Lee, Young-Jin Kim, Seok-Woo Nam
  • Patent number: 7119392
    Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 10, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Seok Kim, Ki-Hyun Hwang, Hyo-Jung Kim, Hyeon-Deok Lee, Seok-Woo Nam
  • Patent number: 7119029
    Abstract: In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: October 10, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Won-Sik Shin, Ki-Hyun Hwang, Jung-Hwan Oh, Hyeon-Deok Lee, Seok-Woo Nam
  • Publication number: 20060160337
    Abstract: In a method of manufacturing a capacitor including a hemispherical grain (HSG) silicon layer, after forming a storage electrode electrically coupled to a contact region of a substrate, the HSG silicon layer is formed on the storage electrode by providing a first gas including silicon and a second gas onto a surface of the storage electrode with a volume ratio of about 1.0:0.1 to about 1.0:5.0. A dielectric layer and a plate electrode are sequentially formed on the HSG silicon layer. A grain size of the HSG silicon layer may be easily adjusted and abnormal growths of the HSG at a lower portion of the storage electrode may be suppressed. Therefore, the HSG silicon layer may be uniformly formed on the storage electrode, and a structural stability of the storage electrode may be improved to prevent electrical defects of the capacitor.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 20, 2006
    Inventors: Young-Jin Kim, Hyeon-Deok Lee, Seok-Woo Nam, Yong-Jae Lee, Hyun-Seok Lim, Wan-Goo Hwang, Jin-Il Lee, Jung-Hwan Oh
  • Publication number: 20060084275
    Abstract: An etch stop layer is formed over a first structure by depositing a metal oxide material over the first structure and annealing the deposited metal oxide material. A second structure is formed over the etch stop layer, and a formation is etched through the second structure using the etch stop layer as an etch stop.
    Type: Application
    Filed: April 11, 2005
    Publication date: April 20, 2006
    Inventors: Young-Sub You, Jae-Young Park, Won-Shik Shin, Hyeon-Deok Lee, Ki-Vin Im, Seok-Woo Nam, Hun-Young Lim, Won-Jun Jang, Yong-Woo Hyung
  • Publication number: 20050221576
    Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.
    Type: Application
    Filed: March 23, 2005
    Publication date: October 6, 2005
    Inventors: Kyoung-Seok Kim, Ki-Hyun Hwang, Hyo-Jung Kim, Hyeon-Deok Lee, Seok-Woo Nam
  • Publication number: 20050153518
    Abstract: A method for forming a capacitor comprises forming a supporting insulating film, an etching stopper film made of alumina series or hafnium oxide series, and a mold insulating film on a surface of a semiconductor substrate having a first structure including conductive plugs surrounded by a first insulating film, patterning the mold insulating film, the etching stopper film and the supporting insulating film to form openings that expose the conductive plugs, forming a storage node conductive film electrically connected to the conductive plugs on the surface of the semiconductor substrate having the openings formed therein and concurrently annealing the etching stopper film, separating the storage node conductive film to form a plurality of storage nodes, exposing at least a part of an outer surface of the storage node by selectively etching remaining mold insulating film, which is exposed by the separated storage node conductive film, until the etching stopper film is exposed, and forming a plurality of plate n
    Type: Application
    Filed: December 15, 2004
    Publication date: July 14, 2005
    Inventors: Young-Sub You, Jung-Hwan Oh, Ki-Su Na, Seok-Woo Nam, Hun-Hyeoung Leam
  • Patent number: 6838719
    Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Ki-Hyun Hwang, Chang-Won Choi, Seok-Woo Nam, Bon-Young Koo, Young-Sub Yu, Han-Jin Lim
  • Publication number: 20040259308
    Abstract: A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySi1-xGex layer stacked on the metallic layer. Methods of forming these capacitors also are provided.
    Type: Application
    Filed: April 13, 2004
    Publication date: December 23, 2004
    Inventors: Eun-ae Chung, Ki-hyun Hwang, Jung-hwan Oh, Hyo-jung Kim, Seok-woo Nam, Won-sik Shin, U-in Chung, Young-sun Kim, Hee-seok Kim, Beom-jun Jin