Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.

Abstract: In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.

Abstract: A method of forming an isolation trench for an integrated circuit device includes forming a trench mask layer on a surface of a semiconductor substrate wherein a portion of the semiconductor substrate is exposed through the trench mask layer. An isolation trench is formed in the exposed portion of the semiconductor substrate, and a nitride liner is formed on surfaces of the isolation trench. A trench isolation layer is formed on the nitride liner wherein the trench isolation layer fills the trench, and the trench mask layer is damaged. The damaged trench mask layer is stripped so that the surface of the semiconductor substrate is exposed.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.

Abstract: A DRAM cell capacitor is provided, having HSG (hemispherical grain) silicon disposed on a selected portion of a storage node. The capacitor resembles a solid cylindrical configuration having a top portion, a side wall, and a top edge portion sloped downward from the top portion to the side wall. HSG silicon is disposed only on the top portion and the side wall, but not on the sloped top edge portion.

Abstract: A method of manufacturing a DRAM cell capacitor is provided wherein a capacitor storage electrode is covered with an HSG (Hemi-Spherical Grain) silicon layer to increase capacitance, but the HSG silicon layer is not formed on the top edge of the capacitor storage electrode.

Abstract: A DRAM cell capacitor is provided wherein a capacitor bottom electrode has an HSG (Hemi-Spherical Grain) layer formed thereon so as to increase capacitance of the capacitor. In the DRAM cell capacitor, the capacitor bottom electrode has an angled shape at a top edge thereof, and the HSG silicon layer is not formed on the top edge of the capacitor bottom electrode. A method for manufacturing the DRAM cell capacitor comprises etching an upper portion of the conductive layer using the photoresist pattern as a mask, and at the same time forming a polymer on both sidewalls of the photoresist pattern to etch the upper portion thereof and thereby to make a top edge of the conductive layer be angled. The method further comprises etching a remaining portion of the conductive layer sing a combination of the photoresist pattern and the polymer as a mask until an upper surface of the interlayer insulating layer is exposed, to thereby form the capacitor bottom electrode.