Abstract: With regard to a function group including all or some functions included in one of multiple binary codes stored in the memory device, a binary code including a first function that is executed at a first timepoint is loaded into a first memory area at a second timepoint that precedes the first time point, thereby minimizing the operation delay time of the memory system, and minimizing the overhead occurring in the processing of calling a specific function.

Abstract: Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number of bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.

Abstract: A memory includes a memory device including plural memory blocks, each memory block including plural pages, and a controller coupled to the memory device and configured to select a target memory block among the plural memory blocks, the target memory block including a first page to an N page (N is a positive integer), and program data in the target memory block, based on a type of the data, either in a first direction from the first page to the N page or in a second direction from the N page to the first page.

Abstract: A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: A memory system includes a memory device including first memory blocks each including a memory cell storing a 1-bit data, and second memory blocks each including a memory cell storing a multi-bit data. The memory system further includes a controller configured to estimate data input/output speed of an operation requested by an external device and to determine, based on the estimated data input/output speed, a buffering ratio of pieces of buffered data, temporarily stored in the first memory blocks, to pieces of inputted data. The controller uses the buffer ratio to determine whether to program pieces of inputted data into the second memory blocks directly or to buffer the inputted data in the first memory blocks before programming it into the second memory blocks.

Abstract: A method to map a plurality of feature maps of a neural network onto a memory hierarchy includes mapping a first feature map of the plurality of feature maps to a memory in a memory hierarchy having available memory space and providing quickest access to the first feature map. The method also includes, when the first feature map expires, removing the first feature map from the memory used to store the first feature map.

Abstract: A memory system includes a memory device including memory blocks and a memory controller configured to control the memory device. The memory device stores a firmware which includes binaries, and the binaries include a first binary and a second binary. The memory controller loads the firmware to a first region in a working memory, loads the first binary to a second region which is included in the first region, and loads the second binary to a third region which is included in the first region and is different from the second region. The memory controller stores information on an entry function corresponding to a target function included in the second binary, in a fourth region which is different from the first region. A start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.

Abstract: A switch control apparatus capable of effectively controlling a switch during a process of controlling the switch provided in a battery pack. When the switch is shifted from a closed state to an open state, the current caused by the generated counter electromotive force is quickly released, thereby quickly shifting the switch to turn on or off. In addition, since the voltage applied to the control unit falls within the rated voltage range, the stability of the switch control circuit may be enhanced.

Abstract: A memory includes a memory device including plural memory blocks, each memory block including plural pages, and a controller coupled to the memory device and configured to select a target memory block among the plural memory blocks, the target memory block including a first page to an N page (N is a positive integer), and program data in the target memory block, based on a type of the data, either in a first direction from the first page to the N page or in a second direction from the N page to the first page.

Abstract: Disclosed is a switch control apparatus capable of effectively controlling a switch during a process of controlling the switch provided in a battery pack. When the switch is shifted from a closed state to an open state, the current caused by the generated counter electromotive force is quickly released, thereby quickly shifting the switch to turn on or off. In addition, since the voltage applied to the control unit falls within the rated voltage range, the stability of the switch control circuit may be enhanced.

Abstract: A memory system comprising: a memory device including a plurality of memory blocks; and a controller suitable for: periodically generating, based on system information periodically inputted from a host, performance information indicating whether an internal operation to be performed on the plurality of memory blocks without a command inputted from the host is performable; accumulatively storing the generated performance information; determining whether the internal operation is performable within a period subsequent to a current period based on the accumulated performance information; and performing the internal operation on the memory blocks during the subsequent period according to a result of the determination.

Abstract: A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.

Abstract: Embodiments of the present invention disclosure relate to a memory system, a memory controller, and an operating method. With regard to a function group including all or some functions included in one of multiple binary codes stored in the memory device, a binary code including a first function that is executed at a first timepoint is loaded into a first memory area at a second timepoint that precedes the first time point, thereby minimizing the operation delay time of the memory system, and minimizing the overhead occurring in the processing of calling a specific function.

Abstract: A memory system includes a memory device including first memory blocks each including a memory cell storing a 1-bit data, and second memory blocks each including a memory cell storing a multi-bit data. The memory system further includes a controller configured to estimate data input/output speed of an operation requested by an external device and to determine, based on the estimated data input/output speed, a buffering ratio of pieces of buffered data, temporarily stored in the first memory blocks, to pieces of inputted data. The controller uses the buffer ratio to determine whether to program pieces of inputted data into the second memory blocks directly or to buffer the inputted data in the first memory blocks before programming it into the second memory blocks.

Abstract: A memory system includes a memory device including a plurality of memory blocks, and a controller configured to determine a data attribute regarding a piece of data stored in a memory block among the plurality of memory blocks, associate the data attribute with a logical address for the piece of data, and transmit the data attribute associated with the logical address to an external device.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: An electronic device, method, and computer readable medium for foveated storage and processing are provided. The electronic device includes a memory, and a processor coupled to the memory. The processor performs head tracking and eye tracking; generates a foveated image from an original image based on the head tracking and the eye tracking; and stores the foveated image using one of: a tile-based method or a frame-based method.