Patents by Inventor Seong-Soon Cho
Seong-Soon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170040254Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Min HWANG, Young-Ho LEE, Seong-Soon CHO, Woon-Kyung LEE
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Patent number: 9553101Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.Type: GrantFiled: April 22, 2014Date of Patent: January 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taekyung Kim, Kwang Soo Seol, Hyunchul Back, Jin-Soo Lim, Seong Soon Cho
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Publication number: 20160343434Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.Type: ApplicationFiled: December 15, 2015Publication date: November 24, 2016Inventors: Joonhee Lee, Jiyoung Kim, Jintaek Park, Seong Soon Cho
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Patent number: 9478560Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.Type: GrantFiled: November 12, 2015Date of Patent: October 25, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Seol, JinTae Kang, Seong Soon Cho
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Patent number: 9466613Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.Type: GrantFiled: May 3, 2016Date of Patent: October 11, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Soo Seol, Seong-Soon Cho
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Publication number: 20160247818Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.Type: ApplicationFiled: May 3, 2016Publication date: August 25, 2016Inventors: Kwang-Soo Seol, Seong-Soon Cho
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Patent number: 9379115Abstract: In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.Type: GrantFiled: November 25, 2013Date of Patent: June 28, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jinhyun Shin, Minchul Kim, Seong Soon Cho, Seungwook Chol
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Patent number: 9356044Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.Type: GrantFiled: December 18, 2015Date of Patent: May 31, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Soo Seol, Seong-Soon Cho
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Publication number: 20160104721Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.Type: ApplicationFiled: December 18, 2015Publication date: April 14, 2016Inventors: Kwang-Soo SEOL, Seong-Soon CHO
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Patent number: 9287167Abstract: A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.Type: GrantFiled: March 6, 2014Date of Patent: March 15, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Seol, Seong Soon Cho, Byungjoo Go, Hongsoo Kim
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Publication number: 20160071879Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.Type: ApplicationFiled: November 12, 2015Publication date: March 10, 2016Inventors: KWANG SOO SEOL, JinTae KANG, SEONG SOON CHO
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Patent number: 9269721Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.Type: GrantFiled: July 23, 2015Date of Patent: February 23, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Seol, JinTae Kang, Seong Soon Cho
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Patent number: 9257572Abstract: A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.Type: GrantFiled: March 15, 2013Date of Patent: February 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-Soo Seol, Seong-Soon Cho
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Publication number: 20150325586Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: KWANG SOO SEOL, JinTae KANG, SEONG SOON CHO
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Patent number: 9129861Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.Type: GrantFiled: October 31, 2014Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Seol, JinTae Kang, Seong Soon Cho
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Publication number: 20150060992Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.Type: ApplicationFiled: September 2, 2014Publication date: March 5, 2015Inventors: KIM TAEKYUNG, KWANG SOO SEOL, SEONG SOON CHO, SUNGHOI HUR, JINTAE KANG
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Publication number: 20150054058Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.Type: ApplicationFiled: October 31, 2014Publication date: February 26, 2015Inventors: Kwang Soo Seol, JinTae Kang, Seong Soon Cho
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Publication number: 20150001460Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.Type: ApplicationFiled: April 22, 2014Publication date: January 1, 2015Inventors: TAEKYUNG KIM, KWANG SOO SEOL, HYUNCHUL BACK, Jin-Soo LIM, SEONG SOON CHO
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Publication number: 20140197546Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.Type: ApplicationFiled: January 16, 2014Publication date: July 17, 2014Inventors: Sung-Min HWANG, Young-Ho LEE, Seong-Soon CHO, Woon-Kyung LEE
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Publication number: 20140187029Abstract: A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Inventors: KWANG SOO SEOL, SEONG SOON CHO, BYUNGJOO GO, HONGSOO KIM