Patents by Inventor Seong-Soon Cho

Seong-Soon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6593188
    Abstract: A non-volatile memory device and a fabrication method thereof are provided. A first polysilicon layer, an inter-gate dielectric layer, a second polysilicon layer and a capping layer are stacked sequentially. A first opening is formed through the inter-gate dielectric layer, the second polysilicon layer and the capping layer, thereby exposing the first polysilicon layer. A second opening is formed through the capping layer, thereby exposing the second polysilicon layer. On the resultant structure, a metal layer is formed and then thermally treated. As a result a metal silicide layer can be formed on the exposed portion of the first polysilicon layer and the exposed portion of the second polysilicon layer.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: July 15, 2003
    Assignee: Samsung Electronics., Ltd.
    Inventor: Seong-Soon Cho
  • Publication number: 20030001196
    Abstract: A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 2, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dal Choi, Jong-Woo Park, Seong-Soon Cho, Chang-Hyun Lee
  • Publication number: 20020123194
    Abstract: A non-volatile memory device and a fabrication method thereof are provided. A first polysilicon layer, an inter-gate dielectric layer, a second polysilicon layer and a capping layer are stacked sequentially. A first opening is formed through the inter-gate dielectric layer, the second polysilicon layer and the capping layer, thereby exposing the first polysilicon layer. A second opening is formed through the capping layer, thereby exposing the second polysilicon layer. On the resultant structure, a metal layer is formed and then thermally treated. As a result a metal silicide layer can be formed on the exposed portion of the first polysilicon layer and the exposed portion of the second polysilicon layer.
    Type: Application
    Filed: September 20, 2001
    Publication date: September 5, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Seong-Soon Cho