Abstract: A display device includes a substrate, a first transistor including a channel on the substrate, a first electrode and a second electrode, and a gate electrode overlapping the channel of the first transistor, a first interlayer insulation layer on the first and second electrodes of the first transistor, a second transistor including a channel disposed on the first interlayer insulation layer, a first electrode and a second electrode of the second transistor, and a gate electrode that overlaps the channel of the second transistor, a first connection electrode disposed on the first interlayer insulation layer, and connected with the first electrode of the first transistor, a gate insulation layer disposed between the first interlayer insulation layer and the first connection electrode, and a second connection electrode that connects the first connection electrode and the first electrode of the second transistor.

Abstract: Provided is a method for performing uplink data compression (UDC) by a user equipment (UE). The method includes receiving configuration information on UDC; generating a first UDC packet by compressing uplink data, based on the configuration information on UDC; transmitting the first UDC packet; receiving, from the base station, packet data convergence protocol (PDCP) layer control information including checksum error information about whether a checksum error has occurred in the first UDC packet; and resetting a UDC buffer used in compressing the uplink data, based on the PDCP layer control information.

Abstract: Disclosed is a 5G or pre-5G communication system for supporting a data transmission rate higher than that of a 4G communication system such as long term evolution (LTE). Disclosed is a method by which a terminal transmits a buffer status report (BSR) in a communication system, including allocating an uplink resource from a base station; comparing the number of padding bits with a value obtained by summing the size of the BSR and the size of a sub-header of the BSR; and transmitting, to the base station according to the comparison result, the BSR including information indicating the presence or absence of a field representing a buffer size for at least one logical channel group (LCG).

Abstract: A 5th Generation (5G) or pre-5G communication system for supporting higher data transmission rates beyond 4th Generation (4G) communication systems such as long term evolution (LTE) systems. A method for transmitting download control information in a communication system is provided. The method includes configuring the control information indicating at least one control channel element (CCE) including at least one resource element group (REG) unit interleaved based on the interleaving information indicated by a higher layer signaling; and transmitting, to a user equipment (UE), the configured control information.

Abstract: A battery module includes a plurality of battery cells; and a module case accommodating the plurality of battery cells, wherein the module case include an upper plate positioned on the plurality of battery cells and a lower plate positioned below the plurality of battery cells, each having a channel in which a coolant flows, the upper plate and the lower plate include a melting spot which melts when heated in a first plate in contact with the plurality of battery cells, and the upper plate includes a vent hole and a first sealing cap in a second plate which faces the first plate, the vent hole through which gas is forced out, and the first sealing cap configured to seal the vent hole and made of a thermomeltable material.

Abstract: A method and apparatus of a user equipment (UE) for transmitting and receiving data in a wireless communication system. The UE receives first time division duplex (TDD) uplink-downlink configuration information for a first cell and second TDD uplink-downlink configuration information for a second cell, determines whether a subframe in the first cell is a special subframe and the subframe in the second cell is a downlink subframe according to the first and second TDD uplink-downlink configuration information, and determine, if the subframe in the first cell is the special subframe and the subframe in the second cell is the downlink subframe, not to receive a signal on the second cell in orthogonal frequency division multiplexing (OFDM) symbols that overlaps with at least one of a guard period (GP) or uplink pilot time slot in the first cell.

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

Abstract: An air conditioner of present invention comprises a housing having an outer panel forming the exterior and an opening formed on the outer panel, a heat exchanger configured to exchange heat with air flowing into the housing, and a door unit configured to open or close the opening by moving forward or backward from the opening through which the heat exchanged air is discharged. Wherein the door unit comprises a door blade configured to open or close the opening, a door operating part configured to move the door blade forward or backward, and a controller configured to control the air discharged from the opening to be moved forward from the opening in a straight line or to be discharged radially from the opening by controlling a distance between the door blade and the opening.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A method of predicting a personalized pollen allergy includes generating a personal allergic symptom diary by recording a daily allergic symptom and daily drug taking information of a user, calculating a daily symptom index using a pollen calendar of a region corresponding to a location of the user and the daily allergic symptom, extracting allergy generation risk grades for each pollen generation species and allergy-sensitive tree species of the user by using the pollen generation species and a pollen generation grade extracted from the pollen calendar, and the daily symptom index, and generating a personalized pollen calendar based on the extracted information, and generating a personalized risk forecast for each city and county for the user by applying the allergy generation risk grades for each pollen generation species and the allergy-sensitive tree species to a Metrological Administration pollen forecast.

Abstract: Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.

Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Abstract: A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.

Abstract: A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.