Abstract: A battery pack includes a battery module assembly having at least one battery cell, a pack case configured to accommodate the battery module assembly, and a barrier unit provided on at least one side of the pack case, configured to discharge a vent gas in the pack case to the outside of the pack case and having at least one blocking baffle disposed obliquely to have a predetermined inclination angle.

Abstract: A battery pack includes a plurality of battery modules each including one or more battery cells to store and release energy, each battery module further including an intake portion and an exhaust portion, an intake duct including an intake channel and communicating with the intake portion of each of the plurality of battery modules, and an exhaust duct including an exhaust channel and communicating with the exhaust portion of each of the plurality of battery modules. Each of the plurality of battery modules further includes an opening/closing member configured to close the intake portion when internal pressure increases.

Abstract: A method of mounting a bus-bar frame includes: forming a plurality of cell lead blocks and a battery cell stacked body by alternately stacking a cell lead block and at least one battery cell; disposing a top cover with respective ends on which a bus-bar frame is installed so as to cover the battery cell stacked body; removing the lead blocks from a space between the battery cell stacked body and the bus-bar frame; and installing the bus-bar frame on the battery cell stacked body by rotating the bus-bar frame. The alternately stacking of the cell lead block and the at least one battery cell includes positioning an electrode lead protruding from each battery cell between neighboring ones of the cell lead blocks.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A method, performed by a user equipment (UE), of transmitting and receiving signals in a wireless communication system, according to an embodiment, includes receiving a logical channel release request from a next-generation node B (gNB), determining a logical channel to release, an operation mode of the logical channel to release, and whether a packet data convergence protocol (PDCP) layer apparatus connected to the logical channel is re-established, based on the logical channel release request, and performing PDCP data recovery based on the determination result.

Abstract: A battery rack includes a plurality of battery modules, each including at least one battery cell, wherein each battery module has at least one venting hole; a rack case accommodating the plurality of battery modules; and a plurality of support brackets disposed in the rack case such that each support bracket supports each battery module and is in communication with the at least one venting hole.

Abstract: A battery pack is configured to improve safety by effectively suppressing heat transfer between battery modules in the present disclosure. A battery pack includes a plurality of battery modules each having one or more battery cells, configured to store and release energy, and stacked in at least one direction; a pack case provided on at least one side of the plurality of battery modules, covering at least a portion of the outside of the plurality of battery modules, and having one or more openings formed therein; and a melting member provided in the opening of the pack case to seal the opening and configured to open the opening by being melted by heat generated from one or more battery modules among the plurality of battery modules.

Abstract: Methods and apparatuses are provided in a wireless communication system. Packet data convergence protocol (PDCP) configuration information that configures a PDCP entity of the terminal to use an uplink data compression (UDC) is received from a base station. The PDCP entity generates a UDC header and a UDC data block, based on the PDCP configuration information. The PDCP entity ciphers the UDC header and the UDC data block. The PDCP entity generates PDCP data including a PDCP header, the ciphered UDC header and the ciphered UDC data block. The generated PDCP data is transmitted to the base station. A header compression is not configured in case that the UDC is configured.

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A method of predicting a personalized pollen allergy includes generating a personal allergic symptom diary by recording a daily allergic symptom and daily drug taking information of a user, calculating a daily symptom index using a pollen calendar of a region corresponding to a location of the user and the daily allergic symptom, extracting allergy generation risk grades for each pollen generation species and allergy-sensitive tree species of the user by using the pollen generation species and a pollen generation grade extracted from the pollen calendar, and the daily symptom index, and generating a personalized pollen calendar based on the extracted information, and generating a personalized risk forecast for each city and county for the user by applying the allergy generation risk grades for each pollen generation species and the allergy-sensitive tree species to a Metrological Administration pollen forecast.

Abstract: Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.

Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Abstract: A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.

Abstract: A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

Abstract: A vehicle predictive control system based on big data includes: a vehicle terminal, which is installed in each of a plurality of vehicles, collecting status information related with an in-vehicle device in a corresponding vehicle to transmit the collected status information in real time, and transmitting problem occurrence information upon problem occurrence of the in-vehicle device; and a big data service provider classifying and storing the status information received from the vehicle terminal as big data, and obtaining a problem occurrence condition based on the status information to transmit information corresponding to the problem occurrence condition to the vehicle terminal when receiving the problem occurrence information of the in-vehicle device from the vehicle terminal of at least some vehicles among the plurality of vehicles.