Patents by Inventor Seung-Hoon Sung

Seung-Hoon Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450527
    Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Willy Rachmady, Marc C. French, Seung Hoon Sung, Jack T. Kavalieros, Matthew V. Metz, Ashish Agrawal
  • Patent number: 11450739
    Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Anand Murthy, Cory Bomberger, Tahir Ghani, Jack Kavalieros, Siddharth Chouksey, Seung Hoon Sung, Biswajeet Guha, Ashish Agrawal
  • Patent number: 11450750
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Tahir Ghani, Jack T. Kavalieros, Gilbert Dewey, Benjamin Chu-Kung, Seung Hoon Sung, Van H. Le, Shriram Shivaraman, Abhishek Sharma
  • Patent number: 11444205
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporatiion
    Inventors: Arnab Sen Gupta, Matthew Metz, Benjamin Chu-Kung, Abhishek Sharma, Van H. Le, Miriam R. Reshotko, Christopher J. Jezewski, Ryan Arch, Ande Kitamura, Jack T. Kavalieros, Seung Hoon Sung, Lawrence Wong, Tahir Ghani
  • Patent number: 11437264
    Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Mo Sung, Jong Woo Sun, Je Woo Han, Chan Hoon Park, Seung Yoon Song, Seul Ha Myung
  • Patent number: 11437472
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Siddharth Chouksey, Glenn Glass, Anand Murthy, Harold Kennel, Jack T. Kavalieros, Tahir Ghani, Ashish Agrawal, Seung Hoon Sung
  • Patent number: 11420903
    Abstract: A glass article includes a first surface, a second surface opposed to the first surface, a first compressive region extending from the first surface to a first compression depth, a second compressive region extending from the second surface to a second compression depth and a tensile region between the first compression depth and the second compression depth. A stress profile of the first compressive region includes a first segment located between the first surface and a first transition point and a second segment located between the first transition point and the first compression depth. A depth from the first surface to the first transition point ranges from 6.1 ?m to 8.1 ?m. A compressive stress at the first transition point ranges from 207 MPa to 254 MPa. A stress-depth ratio of the first transition point ranges from 28 MPa/?m to 35 MPa/?m.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyu In Shim, Seung Kim, Byung Hoon Kang, Young Ok Park, Su Jin Sung
  • Patent number: 11417770
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Nazila Haratipour, Seung Hoon Sung, Benjamin Chu-Kung, Gilbert Dewey, Shriram Shivaraman, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Arnab Sen Gupta
  • Patent number: 11398560
    Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Abhishek Sharma, Jack T. Kavalieros, Sean Ma, Seung Hoon Sung, Nazila Haratipour, Tahir Ghani, Justin Weber, Shriram Shivaraman
  • Publication number: 20220216347
    Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Van H. LE, Ashish AGRAWAL, Seung Hoon SUNG, Abhishek A. SHARMA, Ravi PILLARISETTY
  • Publication number: 20220208991
    Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 30, 2022
    Inventors: Seung Hoon SUNG, Abhishek A. SHARMA, Van H. LE, Gilbert DEWEY, Jack T. KAVALIEROS, Tahir GHANI
  • Publication number: 20220199783
    Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Kevin O'Brien, Chelsey Dorow, Kirby Maxey, Carl Naylor, Tanay Gosavi, Sudarat Lee, Chia-Ching Lin, Seung Hoon Sung, Uygar Avci
  • Publication number: 20220199619
    Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes Hf1-xZxO2, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Seung Hoon Sung, Jack Kavalieros, Uygar Avci, Tristan Tronic, Shriram Shivaraman, Devin Merrill, Tobias Brown-Heft, Kirby Maxey, Matthew Metz, Ian Young
  • Publication number: 20220199833
    Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Shriram Shivaraman, Uygar Avci, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Sou-Chi Chang
  • Publication number: 20220170579
    Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a line passing through a center of the first coupling member with respect to the second coupling member to be positioned in one of up/down/left/right directions, in a test for setting the layout of the brake hose.
    Type: Application
    Filed: January 7, 2021
    Publication date: June 2, 2022
    Applicant: HS R & A Co.,Ltd.
    Inventors: Byeong Ju KIM, Jae Hyeok CHOI, Guk Hyun KIM, Seung Hoon SUNG, Seung Hyo LEE
  • Publication number: 20220153088
    Abstract: A piping system for an air conditioner that includes a refrigerant pipe that is formed of a plastic material and has a multi-layered pipe structure including an outer layer and an inner layer. The piping system provides a fluid flow between parts constituting the air conditioner system. A first flange formed of the plastic material and providing a connection between the refrigerant pipe and components constituting the air conditioner system. A second flange formed of the plastic material and connected to a charging valve for injecting a refrigerant into the refrigerant pipe.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 19, 2022
    Applicant: HS R & A Co.,Ltd.
    Inventors: Jae Hyeok CHOI, Deok Hyun Lim, Young Jun Kim, Seung Hoon Sung, Kwon Sik Hwang
  • Publication number: 20220149209
    Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Gilbert DEWEY, Aaron LILAK, Van H. LE, Abhishek A. SHARMA, Tahir GHANI, Willy RACHMADY, Rishabh MEHANDRU, Nazila HARATIPOUR, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Seung Hoon SUNG, Shriram SHIVARAMAN
  • Patent number: 11322620
    Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Van H. Le, Ashish Agrawal, Seung Hoon Sung, Abhishek A. Sharma, Ravi Pillarisetty
  • Patent number: 11316027
    Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Nazila Haratipour, Tanay Gosavi, I-Cheng Tung, Seung Hoon Sung, Ian Young, Jack Kavalieros, Uygar Avci, Ashish Verma Penumatcha
  • Patent number: 11309400
    Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani