Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: A display device includes a display layer comprising pixels, each of the pixels having at least one thin-film transistor, a connection line electrically connected to the at least one thin-film transistor, the connection line being exposed on a lower surface of the display layer through a first contact hole formed in the display layer, a barrier layer disposed on the lower surface of the display layer and including a second contact hole connected to the first contact hole, a lead line disposed on a lower surface of the barrier layer and electrically connected to the connection line through the second contact hole, a pad part disposed on the lower surface of the barrier layer and electrically connected to the lead line, and a lower film overlapping the lower surface of the barrier layer and the lead line.

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

Abstract: A display module may include a display panel that includes a base layer, a circuit insulating layer, a first electrode, and an emission layer. The circuit insulating layer may include a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness. The first electrode may include a first electrode portion disposed on the first portion and a second electrode portion extending from the first electrode portion and disposed on the second portion. The emission layer may include a first light-emitting portion disposed on the first electrode portion and a second light-emitting portion extending from the first light-emitting portion and disposed on the second electrode portion.

Abstract: A glass article includes a first surface, a second surface opposed to the first surface, a first compressive region extending from the first surface to a first compression depth, a second compressive region extending from the second surface to a second compression depth and a tensile region between the first compression depth and the second compression depth. A stress profile of the first compressive region includes a first segment located between the first surface and a first transition point and a second segment located between the first transition point and the first compression depth. A depth from the first surface to the first transition point ranges from 6.1 ?m to 8.1 ?m. A compressive stress at the first transition point ranges from 207 MPa to 254 MPa. A stress-depth ratio of the first transition point ranges from 28 MPa/?m to 35 MPa/?m.

Abstract: A vehicle steering wheel comprising: a base structure a mobile structure, articulated relative to the base structure so as to be able to move between a first position and a second position, a first mechanism and a second mechanism, each arranged between the base structure, an actuator arranged to generate a movement for driving the first mechanism and the second mechanism, a transmission device comprising at least one cable arranged to transmit the driving movement of the actuator to at least one of the first mechanism or the second mechanism.

Abstract: A method for manufacturing a glass article for a display device includes: providing a LAS-based glass; a first step of immersing the LAS-based glass in a first molten salt; a second step of immersing the LAS-based glass subjected to the first step in a second molten salt; and a third step of immersing the LAS-based glass subjected to the second step in a third molten salt, wherein the concentrations of the first, second, and third molten salts and manufacturing conditions are defined herein.

Abstract: Provided is a reactor and carbonation equipment having the same, and the reactor includes: a plurality of chambers; a support structure for supporting the plurality of chambers; and a plurality of agitators disposed correspondingly to the plurality of chambers to agitate substances disposed in the plurality of chambers, wherein the plurality of chambers may include first to third chambers coupled sequentially to one another in a thickness direction of the reactor, each chamber including a body having a lower portion having the shape of a semi-cylinder and an opening formed on the body to communicate with the neighboring chamber or the outside, the first chamber having a first water introducing pipe for supplying water to the first body, the second chamber having a second water introducing pipe for supplying water to the second body and a first gas introducing pipe for supplying gas to the second body, and the third chamber having a second gas introducing pipe for supplying gas to the third body.

Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.