Abstract: The inventive concept provides a substrate treating method. The substrate treating method includes supplying a liquid to a substrate; and heating the substrate after the supplying the liquid, and wherein the supplying the liquid includes: supplying a first liquid to the substrate; and supplying a second liquid which is different from the first liquid to a substrate to which the first liquid is supplied, and wherein the second liquid is supplied as a test to the substrate and a contact angle between the second liquid which is supplied and the substrate is measured to determine a degree of hydrophilization of the substrate, and a supply mechanism of the second liquid supplied to the substrate is determined based on the degree of hydrophilization of the substrate which is determined, before the supplying the second liquid is performed.

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Abstract: A glass article includes lithium aluminosilicate, includes a first surface, a second surface opposed to the first surface, a first compressive region extending from the first surface to a first compression depth, a second compressive region extending from the second surface to a second compression depth, and, a tensile region disposed between the first compression depth and the second compression depth, where a stress profile of the first compressive region has a first local minimum point at which the stress profile is convex downward and a first local maximum point at which the stress profile is convex upward, where a depth of the first local maximum point is greater than a depth of the first local minimum point, and where a stress of the first local maximum point is greater than a compressive stress of the first local minimum point.

Abstract: A glass article includes a first surface; a second surface opposed to the first surface; a side surface connecting the first surface to the second surface; a first surface compressive region extending from the first surface to a first depth; a second surface compressive region extending from the second surface to a second depth; and a side compressive region extending from the side surface to a third depth, where the first surface and the side surface are non-tin surfaces, the second surface is a tin surface, and a maximum compressive stress of the second surface compressive region is greater than a maximum compressive stress of the first surface compressive region.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: A display module may include a display panel that includes a base layer, a circuit insulating layer, a first electrode, and an emission layer. The circuit insulating layer may include a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness. The first electrode may include a first electrode portion disposed on the first portion and a second electrode portion extending from the first electrode portion and disposed on the second portion. The emission layer may include a first light-emitting portion disposed on the first electrode portion and a second light-emitting portion extending from the first light-emitting portion and disposed on the second electrode portion.

Abstract: A glass article includes a first surface, a second surface opposed to the first surface, a first compressive region extending from the first surface to a first compression depth, a second compressive region extending from the second surface to a second compression depth and a tensile region between the first compression depth and the second compression depth. A stress profile of the first compressive region includes a first segment located between the first surface and a first transition point and a second segment located between the first transition point and the first compression depth. A depth from the first surface to the first transition point ranges from 6.1 ?m to 8.1 ?m. A compressive stress at the first transition point ranges from 207 MPa to 254 MPa. A stress-depth ratio of the first transition point ranges from 28 MPa/?m to 35 MPa/?m.

Abstract: A display device includes a display layer including pixels each including at least one transistor, a connection wiring electrically connected to the at least one transistor and exposed to a lower surface of the display layer through a first contact hole in the display layer, a base member disposed under the display layer and including a first hole exposing the connection wiring exposed to the lower surface of the display layer, a first lower protective layer disposed on a lower surface of the base member and including a second hole overlapping the first hole, a pad portion disposed on a lower surface of the first lower protective layer, and a lead line disposed on the lower surface of the first lower protective layer and electrically connecting the pad portion and the connection wiring. A tiled display device includes multiple display devices.

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Abstract: A glass article includes a first surface; a second surface opposed to the first surface; a side surface connecting the first surface to the second surface; a first surface compressive region extending from the first surface to a first depth; a second surface compressive region extending from the second surface to a second depth; and a side compressive region extending from the side surface to a third depth, where the first surface and the side surface are non-tin surfaces, the second surface is a tin surface, and a maximum compressive stress of the second surface compressive region is greater than a maximum compressive stress of the first surface compressive region.

Abstract: A glass article includes lithium aluminosilicate, includes a first surface, a second surface opposed to the first surface, a first compressive region extending from the first surface to a first compression depth, a second compressive region extending from the second surface to a second compression depth, and, a tensile region disposed between the first compression depth and the second compression depth, where a stress profile of the first compressive region has a first local minimum point at which the stress profile is convex downward and a first local maximum point at which the stress profile is convex upward, where a depth of the first local maximum point is greater than a depth of the first local minimum point, and where a stress of the first local maximum point is greater than a compressive stress of the first local minimum point.

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: Semiconductor devices on a substrate with an alternative crystallographic surface orientation. Example devices includes gate-all-around (e.g., nanoribbon and nanosheet) and forksheet transistors. In an example, a substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating silicon germanium (SiGe) or germanium tin (GeSn) and silicon (Si) semiconductor layers. P-channel transistors may be formed using SiGe or GeSn nanoribbons while n-channel transistors are formed from Si nanoribbons. The crystallographic surface orientation of the SiGe or GeSn nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the SiGe or GeSn nanoribbons and improved device performance.

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.