Abstract: A transistor includes a semiconductor body including a material such as an amorphous or polycrystalline material, for example and a gate stack on a first portion of the body. The gate stack includes a gate dielectric on the body, and a gate electrode on the gate dielectric. The transistor further includes a first metallization structure on a second portion of the body and a third metallization structure on a third portion of the body, opposite to the second portion. The transistor further includes a ferroelectric material on at least a fourth portion of the body, where the ferroelectric material is between the gate stack and the first or second metallization structure.

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

Abstract: Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.

Abstract: Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact may be formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: A jig device for laser welding of the disclosure inclides a jig body having a semi-oval shaped seating groove in which a lower side of a refrigerant pipe to which a charging port is coupled is seated: a first pressing block provided in an upper portion of one side of the jig body and having a first groove part configured to press an upper portion of one side of the refrigerant pipe and an upper portion of one side of a fixing part of the charging port at a lower surface thereof; and a second pressing block provided at an upper portion of the other side of the jig body and having a second groove part configured to press an upper portion of the other side of the refrigerant pipe and an upper portion of the other side of the fixing part of the charging port at a lower surface thereof.

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

Abstract: Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

Abstract: Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

Abstract: Techniques are provided herein to form a forksheet transistor device with a dielectric overhang structure. The dielectric overhang structure includes a dielectric layer that at least partially hangs over the nanoribbons of each semiconductor device in the forksheet transistor and is directly coupled to, or is an integral part of, the dielectric spine between the semiconductor devices. The overhang structure allows for a higher alignment tolerance when forming different work function metals over each of the different semiconductor devices, which in turn allows for narrower dielectric spines to be used. A first gate structure that includes a first work function metal may be formed around the nanoribbons of the n-channel device and a second gate structure that includes a second work function metal may be formed around the nanoribbons of the p-channel device in the forksheet arrangement.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to minimizing sub channel leakage within stacked GAA nanosheet transistors by doping an oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.