Patents by Inventor Seung-hun Lee

Seung-hun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11777001
    Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 3, 2023
    Inventors: Ilgyou Shin, Minyi Kim, Myung Gil Kang, Jinbum Kim, Seung Hun Lee, Keun Hwi Cho
  • Publication number: 20230295500
    Abstract: Proposed is an etching composition capable of adjusting an etching selectivity of a tungsten film with respect to a tungsten film. An etching method using the same etching composition is also proposed. The etching composition includes an inorganic acid, an oxidizing agent, an additive represented by Formula 1, and the remaining proportion of water. The etching composition exhibits remarkable effects of providing a high etching rate for a titanium nitride film and of adjusting the etching selectivity of a titanium nitride film with respect to a tungsten film to be in a range of 1 to 15.
    Type: Application
    Filed: July 5, 2021
    Publication date: September 21, 2023
    Inventors: Seung Hun LEE, Seung Hyun LEE, Seong Hwan KIM, Seung Oh JIN
  • Patent number: 11761140
    Abstract: Provided is a washing machine including a main body having a first inlet, a drum arranged inside the main body to accommodate laundry, and a door configured to open and close the first inlet, wherein the door includes a second inlet to allow laundry to be introduced into the drum while the first inlet closed, an auxiliary door configured to open and close the second inlet, and a restraining device configured to restrain the auxiliary door such that the auxiliary door remains locked onto the door, and the main body includes a pressing device arranged inside the main body and configured to press the restraining device such that the restraining device locks the auxiliary door and to release from the retraining device such that the restraining device unlocks the auxiliary door.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seongwoo Yi, Jun-Young Choi, Minhyung Kim, Joonho Kim, Dong-Il Back, Byoungwoong An, Seung-Hun Lee
  • Publication number: 20230291071
    Abstract: A battery pack may include a pack housing including an accommodation space and a venting passage connecting the accommodation space to outside, a partition wall member partitioning the accommodation space, a plurality of pack units including battery cells, the plurality of pack units disposed in the accommodation space, and a blocking unit provided between the accommodation space and the venting passage, the blocking unit blocking a substance generated in the pack unit from entering the venting passage.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 14, 2023
    Inventors: Ji Hoon LIM, Seung Hun LEE, Tae Gu LEE, Yang Kyu CHOI
  • Publication number: 20230291079
    Abstract: A battery module includes a cell stack in which a plurality of battery cell assemblies are stacked; a busbar assembly electrically connected to the cell stack; and a cover assembly covering the busbar assembly, wherein at least one of the plurality of battery cell assemblies includes at least two battery cells opposing each other; and a support member supporting the at least two battery cells, and wherein the busbar assembly is coupled to the support member.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 14, 2023
    Inventors: Tak Kyung YOO, Seo Roh RHEE, Seung Hun LEE, Yang Kyu CHOI
  • Publication number: 20230291068
    Abstract: A battery pack includes a pack housing having an internal space; and a battery module including a plurality of battery cells and accommodated in the internal space, wherein the pack housing includes a support frame opposing at least one side of the battery module and having a venting passage formed therein, and wherein the support frame includes a plurality of guide blocks inserted into the battery module; and an opening disposed between the plurality of guide blocks and communicating with the venting passage and the internal space.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 14, 2023
    Inventors: Seung Hun LEE, Ji Hoon LIM, Tae Gu LEE, Yang Kyu CHOI
  • Publication number: 20230291059
    Abstract: A battery pack includes a cell assembly; and a pack case accommodating the cell assembly in an internal space, wherein the pack case includes a lower plate having a plate shape and a frame disposed to protrude upwardly from the lower plate, wherein the frame has an inlet through which flame flows from the cell assembly into the internal space of the frame, and a flow path through which the flame flowing in from the inlet flows, wherein the flow path is formed by a partition wall disposed in the length direction of the frame, and wherein at least two or more of the partition walls are spaced apart from each other in the height direction of the frame such that a direction of the flow path is able to be changed.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 14, 2023
    Inventors: Seung Hun LEE, Tae Gu LEE, Ji Hoon LIM, Yang Kyu CHOI
  • Publication number: 20230291036
    Abstract: A battery cell assembly includes a first battery cell, a second battery cell disposed to face the first battery cell, a protective member disposed between the first battery cell and the second battery cell, and a support member coupled to at least one side of the protective member and supporting the protective member. The protective member includes a heat insulating member preventing heat propagation between the first battery cell and the second battery cell.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 14, 2023
    Inventors: Tak Kyung YOO, Seo Roh RHEE, Seung Hun LEE, Yang Kyu CHOI
  • Publication number: 20230291026
    Abstract: A battery pack includes a pack housing including a lower frame and a side frame; and one or more battery modules accommodated in the pack housing. The battery module includes a plurality of cell stacks in which a plurality of battery cells are stacked in a first direction; and a plurality of end plates fastened to the lower frame. The plurality of end plates and the plurality of cell stacks are alternately disposed in the first direction.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 14, 2023
    Inventors: Tak Kyung Yoo, Seo Roh Rhee, Seung Hun Lee, Yang Kyu Choi
  • Publication number: 20230282928
    Abstract: A battery pack includes a plurality of battery modules each including a plurality of battery cells; and a pack housing having a plurality of accommodation spaces in which the plurality of battery modules are accommodated, wherein the pack housing includes a plurality of venting holes disposed on an external surface of the pack housing and configured to discharge gas generated from the plurality of battery modules, and wherein each of the plurality of accommodation spaces is configured to communicate with a different venting hole among the plurality of venting holes.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 7, 2023
    Inventors: Seung Hun LEE, Tak Kyung YOO, Yang Kyu CHOI
  • Publication number: 20230282931
    Abstract: A battery pack includes at least one battery module; and a pack housing having an internal space in which the battery module is accommodated, wherein the at least one battery module includes a cell stack including a plurality of battery cells; and an upper cover covering an upper surface of the cell stack and coupled to the pack housing.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 7, 2023
    Inventors: Seung Hun LEE, Tak Kyung YOO, Yang Kyu CHOI
  • Publication number: 20230282903
    Abstract: A battery device includes a plurality of cell assemblies each including a plurality of battery cells; a housing including an accommodation space in which the plurality of cell assemblies are accommodated; and a cooling plate installed in the housing to cool the plurality of cell assemblies, wherein the cooling plate includes a plurality of seating portions on which the cell assemblies are seated, respectively, and a heat transfer delay portion disposed between the plurality of seating portions and preventing or reducing heat transfer between the seating portions adjacent to each other.
    Type: Application
    Filed: February 23, 2023
    Publication date: September 7, 2023
    Inventors: Seung Hun LEE, Tak Kyung YOO, Yang Kyu CHOI
  • Publication number: 20230275092
    Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: KYUNGIN CHOI, Jinbum Kim, Haejun Yu, Seung Hun Lee
  • Publication number: 20230266672
    Abstract: The present disclosure relates to a process solution composition for EUV photolithography and a pattern forming method using same. The process solution composition includes 0.00001% to 0.01% by weight of a fluorine-based surfactant, 0.00001% to less than 0.01% by weight of a pattern reinforcing agent represented by Formula (1), and 0.00001% to 0.001% by weight of a material selected from the group consisting of triol derivatives, tetraol derivatives, and mixture thereof, and the balance being water.
    Type: Application
    Filed: August 4, 2021
    Publication date: August 24, 2023
    Inventors: Su Jin LEE, Gi Hong KIM, Seung Hun LEE, Seung Hyun LEE
  • Patent number: 11735631
    Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cho-eun Lee, Seok-hoon Kim, Sang-gil Lee, Edward Namkyu Cho, Min-hee Choi, Seung-hun Lee
  • Patent number: 11735663
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
  • Patent number: 11728434
    Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
  • Publication number: 20230255077
    Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Kyoung Seok SON, Myoung Hwa KIM, Jay Bum KIM, Seung Jun LEE, Seung Hun LEE, Jun Hyung LIM
  • Publication number: 20230246029
    Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Inventors: Hyojin KIM, Jihye LEE, Sangmoon LEE, Seung Hun LEE
  • Publication number: 20230226236
    Abstract: The present disclosure relates to a plasma treatment apparatus and a method using the same, and more particularly, to a plasma treatment apparatus for applying, to a target object, such as a biomaterial, characteristics (e.g., removal of organic materials, crosslinking reaction, etching reaction, structural change by surface chemical reaction, sterilization effect, wettability, adhesiveness, bondability, color compatibility, surface reinforcement, modification of surface heat resistance, sterilization, removal of harmful proteins/bacteria, etc.) according to plasma treatment, and a method using the plasma treatment apparatus.
    Type: Application
    Filed: May 28, 2021
    Publication date: July 20, 2023
    Applicant: PLASMAPP CO., LTD.
    Inventors: You Bong LIM, Seung HUn LEE, Jun Young KIM