Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.

Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

Abstract: The present disclosure relates to an anti-glare film including an acrylic substrate and a coating layer located on at least one side of the acrylic substrate, which has a specific rate of change of band area ratio in a graph derived from the result of Raman spectroscopy performed for the coating layer in the thickness direction. It also relates to a polarizing plate, and a display apparatus including the same.

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Abstract: The present disclosure relates to a method for inhibiting a STAT3 activity comprising administering SSu72 protein.

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

Abstract: A rechargeable battery includes an electrode assembly including a first electrode plate, a second electrode plate, and a separator, a case accommodating the electrode assembly and having both ends open, a first cap plate coupled to one end of the case, a second cap plate coupled to the other end of the case, a first cover member disposed to cover the first cap plate and including a first electrode terminal exposed upwardly, and a second cover member disposed to cover the second cap plate and including a second electrode terminal exposed upwardly. A first electrode lead of the electrode assembly passes through the first cap plate to be electrically connected to the first electrode terminal of the first cover member, and a second electrode lead of the electrode assembly passes through the second cap plate to be electrically connected to the second electrode terminal of the second cover member.

Abstract: A processing solution composition for reducing micro-bridge defects in a polyhydroxystyrene-containing photoresist pattern defined by an extreme-ultraviolet exposure source and a method of forming a pattern using the same are proposed. The processing solution composition includes 0.0001 to 1 wt % of an alkaline material, 0.0001 to 1 wt % of a nonionic surfactant having an HLB (Hydrophilic-Lipophilic Balance) value of 9 to 16, and 98 to 99.9998 wt % of water, reduces the number of micro-bridge defects in a polyhydroxystyrene-containing photoresist pattern defined by an extreme-ultraviolet exposure source, and has a low LWR (Line Width Roughness) value, thus effectively improving the uniformity of the pattern.

Abstract: A rechargeable battery includes a case having an internal space having one end thereof open, an electrode assembly disposed in the internal space of the case, and a cap plate coupled to the open case, wherein the electrode assembly has a concave-convex shape in a portion corresponding to the open end when a large surface thereof is viewed.

Abstract: A pixel includes a light emitting element, first through third transistors, sixth through seventh transistors, a ninth transistor, and a capacitor. The first transistor is connected between supply and a second node and controls a driving current supplied to the light emitting element. The second transistor is connected between a third node and a data line. The third transistor is connected between a first node connected to a gate electrode of the first transistor and the second node. The sixth transistor is connected between the supply and a fifth node connected to an electrode of the first transistor. The seventh transistor is connected between the second node and a fourth node connected to an anode of the light emitting element. The ninth transistor is connected between the fifth node and bias. Gate electrodes of the sixth through seventh transistors and the ninth transistor are connected to a same emission line.

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

Abstract: Provided is display device comprising a substrate; a first semiconductor layer disposed on the substrate and having a plurality of transistors; a second semiconductor layer disposed on the first semiconductor layer and having a plurality of transistors; a first data conductive layer disposed on the second semiconductor layer; a first metal layer disposed on the first data conductive layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer includes a first storage electrode and a first input electrode, the second metal layer includes a second storage electrode and a second input electrode, the first storage electrode and the second storage electrode configure a storage capacitor, and the first input electrode and the second input electrode configure an input capacitor.

Abstract: A pixel includes a light emitting element, first through third transistors, sixth through seventh transistors, a ninth transistor, and a capacitor. The first transistor is connected between supply and a second node and controls a driving current supplied to the light emitting element. The second transistor is connected between a third node and a data line. The third transistor is connected between a first node connected to a gate electrode of the first transistor and the second node. The sixth transistor is connected between the supply and a fifth node connected to an electrode of the first transistor. The seventh transistor is connected between the second node and a fourth node connected to an anode of the light emitting element. The ninth transistor is connected between the fifth node and bias. Gate electrodes of the sixth through seventh transistors and the ninth transistor are connected to a same emission line.

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.