Abstract: The present specification relates to a conductive structure body, a method for manufacturing the same, and an electrode and an electronic device including the conductive structure body.

Abstract: A semiconductor package including: a first substrate; a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and a molding layer on the first substrate, the first semiconductor chip and the second substrate, wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate, wherein the molding layer exposes a top surface of the second substrate, and wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.

Abstract: Disclosed are a method for fabricating an enhancement mode transistor material, an enhancement mode transistor material fabricated thereby, an enhancement mode transistor including the same, and an amplifying circuit including the same. The method for fabricating an enhancement mode transistor material includes: a first step of mixing and reacting a solution including a conductive polymer and an ionic reactant including a negative ion that enables deprotonation of the conductive polymer.

Abstract: A wafer processing method of the present invention includes mounting a wafer part on a chuck table, loading the wafer part on the chuck table, spraying, by a spray arm module, a first processing solution onto the wafer part to process the wafer part, spraying, by the spray arm module, a second processing solution onto the wafer part to process the wafer part, drying the wafer part on the chuck table, and unloading the wafer part from the chuck table.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method includes obtaining inter prediction information of a current block and wraparound information from a bitstream, and generating a prediction block of the current block based on the inter prediction information and the wraparound information. The wraparound information may include a first flag specifying whether wraparound motion compensation is enabled for a current video sequence including the current block. The first flag may have a first value specifying that the wraparound motion compensation is disabled, based on that one or more subpicture, which is coded independently and has a width different from a width of a current picture, is present in the current video sequence.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method performed by an image decoding apparatus includes determining a splitting type of a current block, splitting the current block into a plurality of lower-layer blocks based on the splitting type, and decoding the lower-layer blocks. In this case, the current block may be a chroma block, and the determining the splitting type of the current block may be performed by disallowing a predetermined type, in which a width or height of the lower-layer blocks is a predetermined value, among a plurality of splitting types.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a memory cell array in which a plurality of memory cells is vertically stacked to a substrate, wherein each of the memory cells includes: a bit line vertically oriented to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate facing each other with the active layer interposed therebetween, and wherein an edge of the word line and an edge of the back gate have a step shape along a stacking direction of the memory cells.

Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.

Abstract: A video coding device may be configured to perform transform data coding according to one or more of the techniques described herein.

Abstract: A semiconductor device includes: a memory cell array including a vertical conductive line, a horizontal conductive line, and a data storage element; a peripheral circuit portion disposed at a lower-level than the memory cell array; a first bonding pad structure suitable for electrically connecting the vertical conductive line of the memory cell array and the peripheral circuit portion; and an upper pad disposed at a higher level than the memory cell array and coupled to the data storage element.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method performed by an image decoding apparatus may include identifying a prediction mode of a current block, determining a candidate intra prediction mode for the current block, based on a prediction mode of a neighboring block located around the current block, based on the intra prediction mode of the current block being an intra prediction mode, generating a candidate intra prediction mode list of the current block based on the candidate intra prediction mode, and determine an intra prediction mode of the current block based on the candidate intra prediction mode list. In this case, the candidate intra prediction mode may be determined to be a predetermined intra prediction mode, based on the prediction mode of the neighboring block being an MIP mode.

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

Abstract: Disclosed herein are an image encoding/decoding method and apparatus. An image decoding method performed by an image encoding apparatus may include acquiring size information indicating a size of a current slice corresponding to at least a portion of a current picture from a bitstream and determining the size of the current slice based on the size information.

Abstract: Provided are an image encoding/decoding method and device. An image decoding method performed by an image decoding device according to the present disclosure includes the steps of: determining a quantization parameter of the current block on the basis of whether color space conversion is applied to a residual sample of the current block; determining a transform coefficient of the current block on the basis of the quantization parameter; determining the residual sample of the current block by using the transform coefficient; and resetting the value of the residual sample on the basis of whether the color space conversion is applied.

Abstract: An image encoding/decoding method and apparatus are provided. The image decoding method performed by the image decoding apparatus, according to the present disclosure, comprises the steps of: determining a current block by splitting an image on the basis of split information acquired from a bitstream; determining a quantization parameter of the current block; and determining a transform coefficient of the current block on the basis of the quantization parameter.

Abstract: A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.

Abstract: A semiconductor device includes: active layers vertically stacked over a substrate; word lines extending in a direction crossing the active layers over the active layers; a bit line commonly coupled to first sides of the active layers and extending in a direction perpendicular to the substrate; storage nodes of a data storage element that are vertically stacked over the substrate while being coupled to second sides of the active layers, respectively; and vertical isolation layers including air gaps disposed between the bit lines.

Abstract: A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.