Abstract: Provided are an image encoding/decoding method and device. An image decoding method performed by an image decoding device according to the present disclosure includes the steps of: determining a quantization parameter of the current block on the basis of whether color space conversion is applied to a residual sample of the current block; determining a transform coefficient of the current block on the basis of the quantization parameter; determining the residual sample of the current block by using the transform coefficient; and resetting the value of the residual sample on the basis of whether the color space conversion is applied.

Abstract: An image encoding/decoding method and apparatus are provided. The image decoding method performed by the image decoding apparatus, according to the present disclosure, comprises the steps of: determining a current block by splitting an image on the basis of split information acquired from a bitstream; determining a quantization parameter of the current block; and determining a transform coefficient of the current block on the basis of the quantization parameter.

Abstract: A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.

Abstract: A semiconductor device includes: active layers vertically stacked over a substrate; word lines extending in a direction crossing the active layers over the active layers; a bit line commonly coupled to first sides of the active layers and extending in a direction perpendicular to the substrate; storage nodes of a data storage element that are vertically stacked over the substrate while being coupled to second sides of the active layers, respectively; and vertical isolation layers including air gaps disposed between the bit lines.

Abstract: A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.

Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.

Abstract: A payment method for purchase of digital currency includes receiving selection information for selecting a specific payment type among a plurality of different payment types related to digital currency, in relation to a user account; registering a payment condition corresponding to the specific payment type to the user account by using the selection information; and starting an electronic payment process to purchase the digital currency for the user account in response to occurrence of a payment event related to the payment condition at the user account.

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A method for fabricating a semiconductor device includes: forming a sacrificial pad including a plurality of line portions and a plurality of auxiliary lines over a lower structure; forming an etch target layer over the sacrificial pad; forming a plurality of openings by etching the etch-target layer and stopping the etching at the sacrificial pad; forming a pillar filling the openings; forming an isolation trench by etching the etch-target layer and stopping the etching at the sacrificial pad; and forming a pad-type recess by removing the sacrificial pad through the isolation trench.

Abstract: A method for solving a problem and a system thereof are provided. The method includes displaying, by a first terminal device, an embedding content search interface, which is included in a content authoring user interface for creating target content to be transmitted, displaying, by the first terminal device, an indicator of embedding content, determined by user input via the embedding content search interface, in an editing area in the content authoring user interface, transmitting, by the first terminal device, a body of the target content and metadata of the embedding content in response to receipt of input for a “Send” button in the content authoring user interface, and displaying, by a second terminal device, received content with the embedding content embedded therein, wherein the embedding content is embedded in the body of the target content by a server system.

Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.

Abstract: A semiconductor memory device includes: a peripheral circuit portion including an interconnection; first and second word line stacks that are spaced apart from each other over the peripheral circuit portion, the first and second word line stacks including word lines, respectively; an alternating stack of dielectric layers that are positioned over the peripheral circuit portion and disposed between the first and second word line stacks; a first contact plug penetrating the alternating stack to be coupled to the interconnection; a second contact plug coupled to the word lines of the first and second word line stacks; a first line-shape supporter between the first word line stack and the alternating stack, and extending vertically from the peripheral circuit portion; and a second line-shape supporter between the second word line stack and the alternating stack, and extending vertically from the peripheral circuit portion.

Abstract: A video coding device may be configured to perform intra prediction coding according to one or more of the techniques described herein.

Abstract: An image encoding/decoding method and apparatus are provided. The image decoding method includes obtaining, from a bitstream, network abstraction layer (NAL) unit type information of at least one NAL unit including coded image data, determining at least one NAL unit type of one or more slices in the current picture based on the obtained NAL unit type information, and decoding the current picture based on the determined NAL unit type. The current picture is determined to be a random access skipped leading (RASL) picture, based on the determined NAL unit type including a RASL picture NAL unit type (RASL_NUT). When an intra random access point (IRAP) picture associated with the RASL picture is a first picture in decoding order, the RASL picture is decoded, based on the RASL picture including one or more slices having a random access decodable leading (RADL) picture NAL unit type (RADL_NUT).

Abstract: An image encoding/decoding method and apparatus are provided. The image decoding method according to the present disclosure may comprise the steps of: deriving a temporal motion vector predictor for the current block on the basis of a co-located picture for the current block; deriving a motion vector of the current block on the basis of the temporal motion vector predictor; and generating a prediction block of the current block on the basis of the motion vector, wherein the co-located picture is determined on the basis of identification information of the co-located picture, which is included in a slice header of the current slice including the current block, and when the slice header does not include identification information of the co-located picture, the co-located picture is determined on the basis of identification information of the co-located picture, which is included in a picture header of the current picture including the current block.

Abstract: A digital currency payment method for performing a payment related to digital currency used in contents viewing includes monitoring occurrence of a payment event related to a preset payment condition for purchase of the digital currency, in relation to a user account; starting an electronic payment process for purchase of the digital currency with respect to the user account when the payment event has occurred at the user account as a monitoring result; and supplying the digital currency to the user account when the purchase of the digital currency has been completed through the electronic payment process.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method performed by an image decoding apparatus comprises obtaining inter prediction information of a current block and wraparound information from a bitstream, and generating a prediction block of the current block based on the inter prediction information and the wraparound information. The wraparound information may comprise a first flag specifying whether wraparound motion compensation is enabled for a current picture including the current block.

Abstract: Provided is a waveguide module for improving insertion loss and return loss. The waveguide module includes a metal jig including a waveguide through which a radio wave is transmitted and received formed therein, a chip disposed on the waveguide formed in the metal jig and including a plurality of circuits that is configured to transmit and receive radio waves inside the waveguide, and a circuit board configured to provide a bias used for an operation of the chip, wherein the metal jig includes a trench structure to dispose a radio wave absorber on a side surface of the chip in a direction crossing the waveguide.

Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method performed by an image decoding apparatus may comprise parsing weight information specifying a weight for a reference sample from a bitstream according to a weight parameter syntax structure, and decoding a current block by performing inter prediction based on the weight information. The parsing according to the weight parameter syntax structure may comprise obtaining weight number information specifying the number of weight information obtained from the bitstream according to the weight parameter syntax structure and obtaining weight information from the weight parameter syntax structure based on the weight number information.