Patents by Inventor Seung Hwan Kim

Seung Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image encoding/decoding method and apparatus for limiting size of chroma block, and method for transmitting bitstream
    Patent number: 11917147
    Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method performed by an image decoding apparatus includes determining a splitting type of a current block, splitting the current block into a plurality of lower-layer blocks based on the splitting type, and decoding the lower-layer blocks. In this case, the current block may be a chroma block, and the determining the splitting type of the current block may be performed by disallowing a predetermined type, in which a width or height of the lower-layer blocks is a predetermined value, among a plurality of splitting types.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 27, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Jangwon Choi, Jin Heo, Sunmi Yoo, Jungah Choi, Seung Hwan Kim
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20240064959
    Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Inventor: Seung Hwan KIM
  • Memory cell and semiconductor memory device with the same
    Patent number: 11910591
    Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a memory cell array in which a plurality of memory cells is vertically stacked to a substrate, wherein each of the memory cells includes: a bit line vertically oriented to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate facing each other with the active layer interposed therebetween, and wherein an edge of the word line and an edge of the back gate have a step shape along a stacking direction of the memory cells.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: Seung Hwan Kim
  • Memory cell and semiconductor memory device with the same
    Patent number: 11910590
    Abstract: The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: Seung Hwan Kim
  • MEMORY CELL AND MEMORY DEVICE
    Publication number: 20240057309
    Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: Seung Hwan KIM, Dong Sun SHEEN, Su Ock CHUNG, Il Sup JIN, Seon Yong CHA
  • Devices and methods for coding transform data
    Patent number: 11902523
    Abstract: A video coding device may be configured to perform transform data coding according to one or more of the techniques described herein.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 13, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seung-Hwan Kim, Christopher Andrew Segall
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20240049482
    Abstract: A semiconductor device includes: a memory cell array including a vertical conductive line, a horizontal conductive line, and a data storage element; a peripheral circuit portion disposed at a lower-level than the memory cell array; a first bonding pad structure suitable for electrically connecting the vertical conductive line of the memory cell array and the peripheral circuit portion; and an upper pad disposed at a higher level than the memory cell array and coupled to the data storage element.
    Type: Application
    Filed: March 31, 2023
    Publication date: February 8, 2024
    Inventor: Seung Hwan KIM
  • Vertical memory device
    Patent number: 11887654
    Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Seung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
  • Image encoding/decoding method and device for utilizing simplified MPM list generation method, and method for transmitting bitstream
    Patent number: 11889069
    Abstract: An image encoding/decoding method and apparatus are provided. An image decoding method performed by an image decoding apparatus may include identifying a prediction mode of a current block, determining a candidate intra prediction mode for the current block, based on a prediction mode of a neighboring block located around the current block, based on the intra prediction mode of the current block being an intra prediction mode, generating a candidate intra prediction mode list of the current block based on the candidate intra prediction mode, and determine an intra prediction mode of the current block based on the candidate intra prediction mode list. In this case, the candidate intra prediction mode may be determined to be a predetermined intra prediction mode, based on the prediction mode of the neighboring block being an MIP mode.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: January 30, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Jangwon Choi, Jin Heo, Sunmi Yoo, Jungah Choi, Seung Hwan Kim
  • IMAGE ENCODING/DECODING METHOD AND APPARATUS FOR SELECTIVELY ENCODING SIZE INFORMATION OF RECTANGULAR SLICE, AND METHOD FOR TRANSMITTING BITSTREAM
    Publication number: 20240031575
    Abstract: Disclosed herein are an image encoding/decoding method and apparatus. An image decoding method performed by an image encoding apparatus may include acquiring size information indicating a size of a current slice corresponding to at least a portion of a current picture from a bitstream and determining the size of the current slice based on the size information.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 25, 2024
    Inventors: Hendry HENDRY, Seung Hwan KIM, Seethal PALURI
  • Method and device for encoding/decoding image using color space conversion, and method for transmitting bitstream
    Patent number: 11876967
    Abstract: Provided are an image encoding/decoding method and device. An image decoding method performed by an image decoding device according to the present disclosure includes the steps of: determining a quantization parameter of the current block on the basis of whether color space conversion is applied to a residual sample of the current block; determining a transform coefficient of the current block on the basis of the quantization parameter; determining the residual sample of the current block by using the transform coefficient; and resetting the value of the residual sample on the basis of whether the color space conversion is applied.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: January 16, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Jie Zhao, Seung Hwan Kim, Hendry Hendry, Seethal Paluri
  • IMAGE ENCODING/DECODING METHOD AND APPARATUS USING ADAPTIVE TRANSFORM, AND METHOD FOR TRANSMITTING BITSTREAM
    Publication number: 20240015294
    Abstract: An image encoding/decoding method and apparatus are provided. The image decoding method performed by the image decoding apparatus, according to the present disclosure, comprises the steps of: determining a current block by splitting an image on the basis of split information acquired from a bitstream; determining a quantization parameter of the current block; and determining a transform coefficient of the current block on the basis of the quantization parameter.
    Type: Application
    Filed: April 6, 2023
    Publication date: January 11, 2024
    Inventors: Jie ZHAO, Seung Hwan KIM, Hendry HENDRY, Seethal PALURI
  • Memory device
    Patent number: 11871556
    Abstract: A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 9, 2024
    Assignee: SK hynix Inc.
    Inventors: Il Do Kim, Dong Sun Sheen, Seung Hwan Kim
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20230413518
    Abstract: A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.
    Type: Application
    Filed: November 17, 2022
    Publication date: December 21, 2023
    Inventor: Seung Hwan KIM
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20230413517
    Abstract: A semiconductor device includes: active layers vertically stacked over a substrate; word lines extending in a direction crossing the active layers over the active layers; a bit line commonly coupled to first sides of the active layers and extending in a direction perpendicular to the substrate; storage nodes of a data storage element that are vertically stacked over the substrate while being coupled to second sides of the active layers, respectively; and vertical isolation layers including air gaps disposed between the bit lines.
    Type: Application
    Filed: November 17, 2022
    Publication date: December 21, 2023
    Inventors: Seung Hwan KIM, Myoung Jin KANG, Kyung Hoon MIN
  • Semiconductor device and method for fabricating the same
    Patent number: 11844206
    Abstract: The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventor: Seung Hwan Kim
  • SEMICONDUCTOR PACKAGE
    Publication number: 20230395482
    Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.
    Type: Application
    Filed: December 1, 2022
    Publication date: December 7, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jungjoo KIM, Yongkwan LEE, Seung Hwan KIM, Jongwan KIM, Junwoo PARK, Taejun JEON, Junhyeung JO
  • PAYMENT METHOD AND SYSTEM FOR PURCHASING DIGITAL CURRENCY
    Publication number: 20230394447
    Abstract: A payment method for purchase of digital currency includes receiving selection information for selecting a specific payment type among a plurality of different payment types related to digital currency, in relation to a user account; registering a payment condition corresponding to the specific payment type to the user account by using the selection information; and starting an electronic payment process to purchase the digital currency for the user account in response to occurrence of a payment event related to the payment condition at the user account.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 7, 2023
    Inventors: Hyo Jung KIM, Da Young KIM, Yeon Ju CHA, Choon Hae LEE, Ji Hoon HA, Seung Hwan KIM, Yun Il JUNG, Ki Hyun PARK, Chang Min JEON, Se Jin CHA, Jae Han YOON, Yun Yeon CHOI
  • SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    Publication number: 20230386977
    Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 30, 2023
    Applicant: SK hynix Inc.
    Inventors: Seung Hwan KIM, Hyun Chul SEO, Hyeong Seok CHOI, Moon Un HYUN
  • METHOD AND SYSTEM FOR EMBEDDING CONTENT IN EDITING AREA
    Publication number: 20230388258
    Abstract: A method for solving a problem and a system thereof are provided. The method includes displaying, by a first terminal device, an embedding content search interface, which is included in a content authoring user interface for creating target content to be transmitted, displaying, by the first terminal device, an indicator of embedding content, determined by user input via the embedding content search interface, in an editing area in the content authoring user interface, transmitting, by the first terminal device, a body of the target content and metadata of the embedding content in response to receipt of input for a “Send” button in the content authoring user interface, and displaying, by a second terminal device, received content with the embedding content embedded therein, wherein the embedding content is embedded in the body of the target content by a server system.
    Type: Application
    Filed: May 31, 2023
    Publication date: November 30, 2023
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Seung Hwan KIM, Jong Ju LEE