Patents by Inventor Seung Hyuk Kang

Seung Hyuk Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160012896
    Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.
    Type: Application
    Filed: January 21, 2015
    Publication date: January 14, 2016
    Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Matthew Michael Nowak, Seung Hyuk Kang, Xiaonan Chen, Zhongze Wang, Yu Lu
  • Publication number: 20160005955
    Abstract: A magnetic tunnel junction (MTJ) device in a magnetoresistive random access memory (MRAM) and method of making the same are provided to achieve a high tunneling magnetoresistance (TMR), a high perpendicular magnetic anisotropy (PMA), good data retention, and a high level of thermal stability. The MTJ device includes a first free ferromagnetic layer, a synthetic antiferromagnetic (SAF) coupling layer, and a second free ferromagnetic layer, where the first and second free ferromagnetic layers have opposite magnetic moments.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Chando PARK, Matthias Georg GOTTWALD, Kangho LEE, Seung Hyuk KANG
  • Patent number: 9224467
    Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: December 29, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Wuyang Hao, Jungwon Suh, Kangho Lee, Taehyun Kim, Jung Pill Kim, Seung Hyuk Kang
  • Publication number: 20150340101
    Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.
    Type: Application
    Filed: August 6, 2015
    Publication date: November 26, 2015
    Inventors: Xia Li, Seung Hyuk Kang, Xiaochun Zhu
  • Publication number: 20150311429
    Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.
    Type: Application
    Filed: July 9, 2015
    Publication date: October 29, 2015
    Inventors: Xia LI, Kangho LEE, Wei-Chuan CHEN, Yu LU, Chando PARK, Seung Hyuk KANG
  • Publication number: 20150311427
    Abstract: A method for fabricating a perpendicular magnetic tunnel junction (pMTJ) device includes growing a seed layer on a first electrode of the pMTJ device. The seed layer has a uniform predetermined crystal orientation along a growth axis. The method also includes planarizing the seed layer while maintaining the uniform predetermined crystal orientation of the seed layer.
    Type: Application
    Filed: July 17, 2014
    Publication date: October 29, 2015
    Inventors: Matthias Georg GOTTWALD, Jimmy KAN, Kangho LEE, Chando PARK, Seung Hyuk KANG
  • Publication number: 20150303373
    Abstract: A magnetic tunnel junction (MTJ) includes a free layer formed from a ferrimagnetic rare-earth-transition-metal (RE-TM) alloy having the net moment dominated by a sublattice moment of a rare-earth (RE) composition of the RE-TM alloy. The MTJ further includes a pinned layer formed from a rare-earth-transition-metal (RE-TM) alloy having the net moment dominated by a sublattice moment of a rare-earth (RE) composition of the RE-TM alloy, the pinned layer comprising one or more amorphous thin insertion layers such that a net magnetic moment of the free layer and the pinned layer is low or close to zero.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Wei-Chuan CHEN, Xiaochun ZHU, Chando PARK, Seung Hyuk KANG
  • Patent number: 9165630
    Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 20, 2015
    Assignees: QUALCOMM INCORPORATED, INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Seong-Ook Jung, Taehui Na, Jisu Kim, Jung Pill Kim, Seung Hyuk Kang
  • Publication number: 20150279479
    Abstract: An anti-fuse device includes a first electrode, an insulator on the first electrode, a second electrode on the insulator, and selector logic coupled to the second electrode. The device also includes a conductive path between the first and second electrodes. The conductive path may be configured to provide a hard breakdown for one-time programmable non-volatile data storage.
    Type: Application
    Filed: May 20, 2014
    Publication date: October 1, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Xia LI, Wei-Chuan CHEN, Seung Hyuk KANG, Kangho LEE
  • Publication number: 20150280112
    Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Xia LI, Kangho LEE, Wei-Chuan CHEN, Yu LU, Chando PARK, Seung Hyuk KANG
  • Patent number: 9142278
    Abstract: A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: September 22, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Hari M. Rao, Jung Pill Kim, Seung Hyuk Kang
  • Patent number: 9142762
    Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: September 22, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xia Li, Kangho Lee, Wei-Chuan Chen, Yu Lu, Chando Park, Seung Hyuk Kang
  • Publication number: 20150263266
    Abstract: An apparatus includes a perpendicular magnetic anisotropy magnetic tunnel junction (pMTJ) device. The pMTJ device includes a storage layer and a reference layer. The reference layer includes a portion configured to produce a ferrimagnetic effect. The portion includes a first layer, a second layer, and a third layer. The second layer is configured to antiferromagnetically (AF) couple the first layer and the third layer during operation of the pMTJ device.
    Type: Application
    Filed: August 15, 2014
    Publication date: September 17, 2015
    Inventors: Matthias Georg Gottwald, Chando Park, Xiaochun Zhu, Kangho Lee, Seung Hyuk Kang
  • Patent number: 9135976
    Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Wenqing Wu, Kendrick Hoy Leong Yuen, Xiaochun Zhu, Seung Hyuk Kang, Matthew Michael Nowak, Jeffrey Alexander Levin, Robert P. Gilmore, Nicholas Ka Ming Yu
  • Publication number: 20150249209
    Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Yu LU, Xia LI, Seung Hyuk KANG, Shiqun GU
  • Patent number: 9111623
    Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 18, 2015
    Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seong-Ook Jung, Taehui Na, Ji-su Kim, Jung Pill Kim, Seung Hyuk Kang
  • Publication number: 20150228891
    Abstract: A magnetic tunnel junction (MTJ) and methods for fabricating a MTJ are described. An MTJ includes a fixed layer and a barrier layer on the fixed layer. Such an MTJ also includes a free layer interfacing with the barrier layer. The free layer has a crystal structure in accordance with the barrier layer. The MTJ further includes an amorphous capping layer interfacing with the free layer.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 13, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Chando PARK, Kangho LEE, Seung Hyuk KANG
  • Publication number: 20150228322
    Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 13, 2015
    Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM Incorporated
    Inventors: Seong-Ook JUNG, Taehui NA, Ji-su KIM, Jung Pill KIM, Seung Hyuk KANG
  • Patent number: 9082962
    Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: July 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Seung Hyuk Kang, Xia Li, Wei-Chuan Chen, Kangho Lee, Xiaochun Zhu, Wah Nam Hsu
  • Patent number: 9070870
    Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: June 30, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Xia Li, Wei-Chuan Chen, Seung Hyuk Kang