Patents by Inventor Seung Yeop Lee

Seung Yeop Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11195827
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Jin Woo Kim, Hyun Duck Lee, Seung Yeop Lee, Ju Hyeong Lee
  • Patent number: 11164833
    Abstract: Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jo Park, Seung Yeop Lee
  • Patent number: 11158626
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Hee Jeong Son, Ki Ryong Jung, Seung Yeop Lee
  • Patent number: 11152335
    Abstract: A stack package includes a supporting substrate that supports first and second semiconductor dies. The supporting substrate is disposed on a package substrate and is supported by first and second connection bumps. Redistributed line (RDL) patterns are disposed on the supporting substrate to electrically connect the first semiconductor die to the first and second connection bumps. The second semiconductor dies are connected to the package substrate by bonding wires.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Seung Yeop Lee
  • Publication number: 20210187491
    Abstract: Disclosed is a method for preparing a titanium solid catalyst supported on magnesium dichloride that may be used to prepare ultra-high molecular weight polyethylene having a high apparent density. Performing a polymerization reaction using a solid catalyst containing titanium tetrachloride and a phthalate compound may allow ultra-high molecular weight polyethylene having uniform particle size and high apparent density to be prepared.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 24, 2021
    Inventors: Seung Yeop LEE, Jin Woo LEE
  • Publication number: 20210189026
    Abstract: Disclosed is a method for preparing a solid catalyst capable of controlling a molecular weight distribution and polydispersity according to an organic compound as used in a polymerization reaction, in which the solid catalyst contains titanium tetrachloride and a diester or diether organic compound. The catalyst having excellent polymerization activity, and allowing uniform particle size and high apparent density of the ultra-high molecular weight polyethylene, and easily controlling the molecular weight distribution and polydispersity of the ultra-high molecular weight polyethylene may be prepared simply and efficiently.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 24, 2021
    Inventors: Seung Yeop LEE, Jin Woo LEE
  • Patent number: 11004831
    Abstract: A stack package includes a package substrate and a fan-out sub-package mounted on the package substrate using first and second connection bumps. The fan-out sub-package includes a first semiconductor die and redistributed line (RDL) patterns. Second semiconductor dies are stacked on the package substrate to provide a first step structure, and third semiconductor dies are stacked on the second semiconductor dies to provide a second step structure. The second and third semiconductor dies are connected to the package substrate by bonding wires.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Seung Yeop Lee
  • Publication number: 20210104479
    Abstract: Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.
    Type: Application
    Filed: March 31, 2020
    Publication date: April 8, 2021
    Inventors: Young Jo PARK, Seung Yeop LEE
  • Publication number: 20200395340
    Abstract: A stack package includes a supporting substrate that supports first and second semiconductor dies. The supporting substrate is disposed on a package substrate and is supported by first and second connection bumps. Redistributed line (RDL) patterns are disposed on the supporting substrate to electrically connect the first semiconductor die to the first and second connection bumps. The second semiconductor dies are connected to the package substrate by bonding wires.
    Type: Application
    Filed: November 27, 2019
    Publication date: December 17, 2020
    Applicant: SK hynix Inc.
    Inventor: Seung Yeop LEE
  • Publication number: 20200350290
    Abstract: A stack package includes a package substrate and a fan-out sub-package mounted on the package substrate using first and second connection bumps. The fan-out sub-package includes a first semiconductor die and redistributed line (RDL) patterns. Second semiconductor dies are stacked on the package substrate to provide a first step structure, and third semiconductor dies are stacked on the second semiconductor dies to provide a second step structure. The second and third semiconductor dies are connected to the package substrate by bonding wires.
    Type: Application
    Filed: November 20, 2019
    Publication date: November 5, 2020
    Applicant: SK hynix Inc.
    Inventor: Seung Yeop LEE
  • Publication number: 20200258646
    Abstract: Mineralogical method and apparatus for removal of cesium ion in aqueous solution are provided. In particular, a mineralogical method for removal of cesium ion in aqueous solution including controlling a temperature of radioactive wastewater containing cesium from 25 to 45° C., controlling an initial pH of the radioactive wastewater from 6.0 to 8.5, and adding iron(II) and sulfide(?II) containing sulfur in the ?2 oxidation state to the radioactive wastewater, to convert the cesium ion in aqueous solution into a cesium mineral, and a mineralogical apparatus for removal of cesium ion in aqueous solution, capable of being applied to such a method, are provided.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 13, 2020
    Inventors: Seung Yeop Lee, Hyo Jin Seo, Jae Kwang Lee, Min Hoon Baik
  • Publication number: 20190379204
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.
    Type: Application
    Filed: January 25, 2019
    Publication date: December 12, 2019
    Applicant: SK hynix Inc.
    Inventors: Chang Hwi LEE, Jin Woo KIM, Hyun Duck LEE, Seung Yeop LEE, Ju Hyeong LEE
  • Patent number: 10337035
    Abstract: The present invention provides a fed-batch culture method comprising a step of fed-batch-feeding a carbon source base and a base in such a manner that the pH level can be maintained at a level suitable for the growth of microorganisms for fermentation of a carbon source. The present invention also provides a method for preparing organic acids using the fed-batch culture method. The present invention fed-batch-feeds a neutralizing agent such as ammonium bicarbonate, ammonium carbonate or alkali metal-containing weak base, and a carbon source substrate in preparing organic acids by microorganism fermentation. Thus, a pH level suitable for the survival of microorganisms for carbon source fermentation can be maintained, and the speed of injecting the carbon source base which is the source material can be appropriately adjusted.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 2, 2019
    Assignees: SK INNOVATION CO., LTD., SK ENERGY CO., LTD.
    Inventors: Jae Yeon Park, Sin Young Kang, Woo Chan Park, Min Su Koo, In Ho Cho, Joong Min Park, Seung Yeop Lee, Dong Hyun Kim
  • Patent number: 10262972
    Abstract: A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung Yeop Lee, Jin Kyoung Park
  • Publication number: 20180350797
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.
    Type: Application
    Filed: January 19, 2018
    Publication date: December 6, 2018
    Inventors: Chang Hwi LEE, Hee Jeong SON, Ki Ryong JUNG, Seung Yeop LEE
  • Publication number: 20180342481
    Abstract: A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.
    Type: Application
    Filed: December 1, 2017
    Publication date: November 29, 2018
    Applicant: SK hynix Inc.
    Inventors: Seung Yeop LEE, Jin Kyoung PARK
  • Publication number: 20180066602
    Abstract: An engine may include a cylinder bore configured to have a combustion chamber formed by setting a top section in which a top dead center is formed, a bottom section in which a bottom dead center is formed, and a middle section H formed between the top section and the bottom section and reduce a shearing resistance by a texturing pattern formed in the middle section H.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 8, 2018
    Applicant: Hyundai Motor Company
    Inventors: Jun-Sik PARK, Sun-Joon MIN, Hee-Gone KIM, Nam-Doo LEE, Ho-Hwan KIM, Tae-Kyun AN, Seung-Yeop LEE, Do-Hyung KIM, Tae-Won LEE
  • Patent number: 9888567
    Abstract: A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. The second conductive pattern includes a second sliding contact portion overlapping with the first sliding contact portion and the second conductive pattern includes a second extension portion. The second sliding contact portion is in contact with the first sliding contact portion and is movable on the first sliding contact portion for a sliding motion. The first and second conductive patterns are embedded in the dielectric layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Yeop Lee, Joo Hyun Kang, Jong Hoon Kim, Han Jun Bae
  • Publication number: 20180002210
    Abstract: Provided are a biomineralogical method for removing cesium ions. The method for removing cesium ions, the method comprising: adding metal-reducing bacteria, an iron source, and a sulfur source into a solution containing the cesium ions to convert the cesium ions into a solid mineral incorporating cesium. The method for removing cesium ions according to the present invention has advantages in that the cesium ions may be removed with high efficiency and small volume even in the case in which competing ions are present at a high concentration like sea water.
    Type: Application
    Filed: March 28, 2017
    Publication date: January 4, 2018
    Inventors: Seung Yeop LEE, Jin Ha HWANG, Min-Hoon BAIK, Bum Kyoung SEO, Minhee LEE
  • Publication number: 20170064832
    Abstract: A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. The second conductive pattern includes a second sliding contact portion overlapping with the first sliding contact portion and the second conductive pattern includes a second extension portion. The second sliding contact portion is in contact with the first sliding contact portion and is movable on the first sliding contact portion for a sliding motion. The first and second conductive patterns are embedded in the dielectric layer.
    Type: Application
    Filed: January 7, 2016
    Publication date: March 2, 2017
    Inventors: Seung Yeop Lee, Joo Hyun Kang, Jong Hoon Kim, Han Jun Bae