Abstract: A single ended highly linear power amplifier includes a component, a 1st transistor pair, and a 2nd transistor pair. The 1st and 2nd transistor pairs are coupled in series with the component, which may be a resistor, inductor and/or linearly loaded transistor, where the node coupling the component to the 1st and 2nd transistor pairs provides the output of the single-ended highly linear power amplifier. The 1st transistors of the 1st and 2nd transistor pairs are coupled to receive an input signal. The 2nd transistors of the 1st and 2nd transistor pairs are each coupled to receive a separate enable signal. The transistor pairs are enabled via their corresponding enable signal to change the gain of the power amplifier with negligible effects on the linearity of the power amplifier. A differential power amplifier includes the single ended power amplifier and a complimentary mirror image of the single ended power amplifier.

Abstract: An on chip diversity antenna switch includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is operably coupled to a pin associated with a first antenna, to a transmit path and to receive a transmit receive (T/R) control signal. The second switch is operably coupled to the pin associated with the first antenna, to a receive path, and to receive the T/R control signal. The third switch is operably coupled to a pin associated with a second antenna, the transmit path, and to receive the T/R control signal. The fourth switch is operably coupled to the pin associated with the second antenna, to the receive path, and to receive the T/R control signal. Based on the T/R control signal, the first or second antenna is coupled to the transmit or receive path via a single switch.

Abstract: A programmable multi-stage amplifier includes a 1st programmable amplifier, a 2nd programmable amplifier, and a control module. The 1st and 2nd programmable amplifiers are coupled in series to amplify an input signal. Each of the 1st and 2nd programmable amplifiers is operably coupled to receive independent gain control signals from the control module. The control module generates the gain control signals by determining the overall gain desired for the programmable multi-stage amplifier and a corresponding gain for each of the 1st and 2nd programmable amplifiers. The factors in which the control module makes this determination are based on an optimization of at least one of the power level of the programmable multi-stage amplifier, the noise factor for the programmable multi-stage amplifier, and/or linearity of the programmable multi-stage amplifier.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1st input, 2nd input and an output, where the 1st input is operably coupled to receive the high frequency signal. The transistor has an input, a first node, and a second node, where the input is coupled to the output of the amplifier, the second node is coupled to a supply voltage, and the first node is coupled to the 2nd input of the amplifier. The capacitor is operably coupled to the first node of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.

Abstract: A linear high powered integrated circuit amplifier includes a plurality of power amplifiers, balanced integrated circuit coupling, and a combining circuit. The balanced integrated circuit coupling couples a signal to the plurality of power amplifiers to the up-conversion module such that the power amplifiers amplify the signal to produce a plurality of amplified radio frequency (RF) signals. The combining circuit is operably coupled to combine the plurality of amplified RF signals to produce a high-powered amplified signal.

Abstract: A RFIC includes a die and a package. The die contains a radio frequency (RF) input/output (I/O) section, an RF-to-baseband conversion section, and a baseband processing section. The package includes a plurality of connections for connecting to the die. The die is positioned within the package to minimize adverse affects of parasitics components of coupling the RFIO section to an antenna. The positioning of the die within the package may be offset from the center of the package and/or positioned at the edge of the package.

Abstract: A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1st input, 2nd input and an output, where the 1st input is operably coupled to receive the high frequency signal. The transistor has a gate, a drain, and a source, where the gate is coupled to the output of the amplifier, the source is coupled to a supply voltage, and the drain is coupled to the 2nd input of the amplifier. The capacitor is operably coupled to the drain of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.

Abstract: A linear high powered integrated circuit transmitter includes an up-conversion module, a plurality of power amplifiers, balanced integrated circuit coupling, and a combining circuit. The up-conversion module is operably coupled to produce a differential up-converted signal by mixing one or more local oscillations with a low intermediate frequency (IF) signal. The balanced integrated circuit coupling couples the plurality of power amplifiers to the up-conversion module such that the power amplifiers amplify the up-converted signal to produce a plurality of amplified radio frequency (RF) signals. The combining circuit is operably coupled to combine the plurality of amplified RF signals to produce a transmit RF signal.

Abstract: A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the programmable mixer are set to zero, or to a known state and the local oscillator is set to a calibration frequency. Then, one of a plurality of known calibration states of the programmable mixer is entered and the local oscillator feedthrough is measured. For each of a plurality of operating states an amplified output of the programmable mixer is measured. In one operation, the state of the programmable mixer in which the programmable mixer operates during a next operation phase is the state that produces minimal local oscillator feedthrough. In another operation, operation continues until a state is found that produces a local oscillation feedthrough that meets an operating criteria and that state is used during the next operation phase.

Abstract: In one embodiment, the present invention is a low-power, and high performance receiver including an IF demodulator for high data rate, frequency modulated systems, such as Bluetooth. The IF demodulator is implemented in analog domain for simplicity and lower power consumption and operates at an IF frequency. An IF demodulator comprises: a first IF differentiator for differentiating an I signal; a second IF differentiator for differentiating a Q signal; a cross-coupled multiplier for multiplying the differentiated I signal with the Q signal and multiplying the differentiated Q signal with the I signal to extract frequency information from the I signal and the Q signal; and a slicer for converting the frequency information to digital data.

Abstract: A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the programmable mixer are set to zero, or to a known state and the local oscillator is set to a calibration frequency. Then, one of a plurality of known calibration states of the programmable mixer is entered and the local oscillator feedthrough is measured. For each of a plurality of operating states an amplified output of the programmable mixer is measured. In one operation, the state of the programmable mixer in which the programmable mixer operates during a next operation phase is the state that produces minimal local oscillator feedthrough. In another operation, operation continues until a state is found that produces a local oscillation feedthrough that meets an operating criteria and that state is used during the next operation phase.

Abstract: In one embodiment, the present invention is a low-power, and high performance receiver including an IF demodulator for high data rate, frequency modulated systems, such as Bluetooth. The IF demodulator is implemented in analog domain for simplicity and lower power consumption and operates at an IF frequency. An IF demodulator comprises: a first IF differentiator for differentiating an I signal; a second IF differentiator for differentiating a Q signal; a cross-coupled multiplier for multiplying the differentiated I signal with the Q signal and multiplying the differentiated Q signal with the I signal to extract frequency information from the I signal and the Q signal; and a slicer for converting the frequency information to digital data.

Abstract: A method for direct tuning of a radio receiver begins by providing a plurality of frequency-dependent control input signals to an input of the radio receiver.

Abstract: A tuned transformer balun circuit includes a transformer balun, a first tuning capacitor, a second tuning capacitor, and a third tuning capacitor. A first plate of the first tuning capacitor is operably coupled to a first node of the differential winding and a second plate of the first tuning capacitor is operably coupled to a circuit ground. A first plate of the tuning capacitor is operably coupled to a second node of the differential winding and a second plate of the second tuning capacitor is operably coupled to the circuit ground. A first plate of the third tuning capacitor is operably coupled to a first node of the single-end winding and the second plate of the third tuning capacitor is operably coupled to transceiver radio frequency signals, wherein, based on loading of the single-ended winding and the differential winding, the first, second, and third tuning capacitors resonate with the transformer balun to provide efficient energy transfer from the transmitter section to the antenna.

Abstract: A transceiver front end includes a transmit/receive (T/R) switch, a first balun, a second balun, a low noise amplifier, a power amplifier, and compensation circuitry. The T/R switch is operably coupled to an antenna for receiving inbound radio frequency (RF) signals and for transmitting outbound RF signals. The first balun includes a single ended winding and a differential winding, where the single ended winding is operably coupled to the T/R switch. The second balun includes a single ended winding and a differential winding, where the single ended winding is operably coupled to the T/R switch. The low noise amplifier is operably coupled the differential winding of the first balun. The power amplifier is operably coupled to the differential winding of the second balun. The compensation circuitry is operably coupled to the first balun to compensate for at least one of phase imbalance, amplitude imbalance, and impedance imbalance of the first balun.

Abstract: A high frequency peak detector includes an operational amplifier, a transistor, a capacitor, and an average to peak conversion module. A first inverting input of the operational amplifier receives a high frequency input signal, a second inverting input of the operational amplifier receives a common mode voltage of the high frequency signal, and a non-inverting input of the operational amplifier is coupled to the output of the operational amplifier. A gate of the transistor is operably coupled to the output of the operational amplifier and the source of the transistor is operably coupled to a power supply. The capacitor is operably coupled to the drain of the transistor to provide an analog signal representing an average peak to common mode value of the high frequency signal and to a circuit ground. The average to peak conversion module determines a peak value of the high frequency signal based on the analog signal and the common mode value.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method and apparatus for direct tuning of a component embedded within an integrated circuit includes processing that begins by providing a plurality of frequency dependent control input signals to an input of the integrated circuit. The processing continues for each of the plurality of frequency dependent control input signals by incrementally adjusting the power level of each frequency dependent controlled input signal until the signal strength of an output of the integrated circuit is at a desired signal strength level. The corresponding power level is recorded to produce an adjusted power level for the frequency dependent control input signal. The adjusted power level of each of the plurality of frequency dependent control input signals is plotted to produce a signal strength to frequency relationship. The processing continues by comparing the signal strength to frequency relationship with a desired signal strength to frequency relationship.