Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: An RFIC includes a baseband processing module, a digital to analog converter, an analog to digital converter, a radio module, and a border section. The border section is fabricated on the substrate, wherein the border section physically separates the radio module from the baseband processing module, the digital to analog converter, and the analog to digital converter, wherein the border section includes noise suppression circuitry operably coupled to convert outbound baseband signals into low noise outbound baseband signals and to convert low noise inbound baseband signals into inbound baseband signals.

Abstract: A high frequency integrated circuit (IC) pad configuration includes a first IC pad, an inductor, and a second IC pad. The first IC pad is directly coupled to input or output a high frequency signal, wherein no electrostatic discharge (ESD) protection circuitry is directly coupled to the first IC pad. The inductor includes a first node and a second node, wherein the first node of the inductor is directly coupled to the first IC pad, and wherein the inductor has a high impedance with respect to a desired input or desired output impedance of the first IC pad at frequencies of the high frequency signal. The second IC pad is directly coupled to a power connection, to the second node of the inductor, and to an ESD protection circuit, wherein the inductor and the ESD protection circuit of the second IC pad substantially provides ESD protection for the first IC pad.

Abstract: A radio frequency integrated circuit (RFIC) includes a digital to analog converter, an analog to digital converter, and a radio module. The digital to analog converter (DAC) is operably coupled to convert outbound symbols into outbound baseband signals, wherein the digital to analog converter is fabricated within a DAC portion of a substrate of the RFIC. The analog to digital converter (ADC) is operably coupled to convert inbound baseband signals into inbound symbols, wherein the analog to digital converter is fabricated within an ADC portion of the substrate. The radio module is operably coupled to convert the outbound baseband signals into outbound radio frequency (RF) signals and to convert inbound RF signals into the inbound baseband signals. The radio module is fabricated within a radio portion of the substrate, wherein the DAC portion of the substrate is physically between the ADC portion and the radio portion of the substrate.

Abstract: A low loss transmit/receive switch includes a 1st antenna capacitive coupling circuit, a 2nd antenna capacitive coupling circuit, an antenna selection circuit, a 1st inductive coupling circuit, and a 2nd inductive coupling circuit. The 1st antenna capacitive coupling circuit is operably coupled to a 1st antenna. The 2nd antenna capacitive coupling circuit is operably coupled to a 2nd antenna. The antenna selection circuit is operably coupled to enable the 1st or the 2nd antenna in accordance with an antenna selection signal. The 1st inductive coupling circuit is operably coupled to the 1st and the 2nd antenna capacitive coupling circuits and to an output of a power amplifier. The 2nd inductive coupling circuit is operably coupled to the 1st and the 2nd antenna capacitive coupling circuits and to an input of the low noise amplifier.

Abstract: A RFIC includes a die and a package. The die contains a radio frequency (RF) input/output (I/O) section, an RF-to-baseband conversion section, and a baseband processing section. The package includes a plurality of connections for connecting to the die. The die is positioned within the package to minimize adverse affects of parasitics components of coupling the RFIO section to an antenna. The positioning of the die within the package may be offset from the center of the package and/or positioned at the edge of the package.

Abstract: A method for packaging a radio frequency integrated circuit (RFIC) in multiple packages begins by determining a 1st position of the RFIC die in a 1st package wherein the positioning is such to minimize adverse affects of parasitic components of coupling between the radio frequency input/output section and an antenna. Once the position within the 1st package has been determined, the corresponding parasitics are measured to determine their values. The processing then continues by determining a 2nd position of the RFIC die in a 2nd package based on the values of the parasitic components. Accordingly, the 2nd position places the die within the 2nd package such that the parasitic components of coupling between the RF I/O section to the antenna within the 2nd package substantially matches the parasitic components of coupling the RFIO section to the antenna in the 1st package. Accordingly, different packages may be used with the same RFIC die, while maintaining the desired noise reduction.

Abstract: A radio frequency integrated circuit (RFIC) having sectional electrostatic discharge (ESD) protection includes an analog receive section, an analog transmit section, a digital section, a first inductor assembly and a second inductor assembly. The analog receive section is operably coupled to convert inbound RF signals into inbound low IF signals and includes an analog receive ground connection. The analog transmit section is operably coupled to convert outbound low IF signals into outbound RF signals and includes an analog transmit ground connection. The digital section is operably coupled to convert the inbound low IF signals into inbound digital baseband signals and to convert outbound digital baseband signals into the outbound low IF signals, wherein the digital section has a digital ground connection. The first inductor assembly operably couples the analog receive ground connection to the digital ground connection.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: A method for adjusting a programmable mixer of a local oscillation module to reduce local oscillation leakage begins by determining at least one of: DC offset of an input signal of the programmable mixer and process mismatches between a first mixing stage and a second mixing stage. The method continues by determining operational characteristics mismatch between the first mixing stage and the second mixing stage based on the at least one of the DC offset and process mismatches. The method continues by generating a control signal to substantially compensate for the operational characteristics mismatch. The method continues by providing the control signal to a compensation module, wherein the compensation module modifies operational characteristics of at least one of the first and second mixing stages based on the control signal such that the operational characteristics of the first mixing stage substantially equals the operational characteristics of the second mixing stage.

Abstract: A high gain, highly linear mixer includes an input section, mixing section, at least one tuning component, and at least one stand by current source. The input section is operably coupled to receive an input voltage signal and perform a linear transconductance thereon to produce an input current signal. The mixing section is operably coupled to mix a local oscillation with the input current to produce a mixed current signal. The tuning component is operably coupled to the mixing section and to convert the mixed current signal into a mixed voltage signal that function as the output of the mixer. The standby current source is operably coupled to the mixing section and provides a standby current to the mixing section.

Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.

Abstract: An on chip diversity antenna switch includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is operably coupled to a pin associated with a first antenna, to a transmit path and to receive a transmit receive (T/R) control signal. The second switch is operably coupled to the pin associated with the first antenna, to a receive path, and to receive the T/R control signal. The third switch is operably coupled to a pin associated with a second antenna, the transmit path, and to receive the T/R control signal. The fourth switch is operably coupled to the pin associated with the second antenna, to the receive path, and to receive the T/R control signal. Based on the T/R control signal, the first or second antenna is coupled to the transmit or receive path via a single switch.

Abstract: Determination of a received signal strength indication in a direct conversion receiver begins by determining, at a given time, a 1st value to be the larger of the in-phase component of the received signal and the quadrature component of the received signal. The direct conversion receiver then determines a 2nd value at the given time to be the smaller of the in-phase component of the received signal and the quadrature component of the received signal. As such, at a given time, the 1st and 2nd values correspond to the greater and lesser of the in-phase component and quadrature component, respectively. Having obtained these values, the direct conversion receiver then determines the received signal strength indication based on the 1st value, the 2nd value and an offset value. The offset value provides a scaling of the RSSI value based on the range of the RSSI values.

Abstract: A linear high powered integrated circuit transmitter includes an up-conversion module, a plurality of power amplifiers, balanced integrated circuit coupling, and a combining circuit. The up-conversion module is operably coupled to produce a differential up-converted signal by mixing one or more local oscillations with a low intermediate frequency (IF) signal. The balanced integrated circuit coupling couples the plurality of power amplifiers to the up-conversion module such that the power amplifiers amplify the up-converted signal to produce a plurality of amplified radio frequency (RF) signals. The combining circuit is operably coupled to combine the plurality of amplified RF signals to produce a transmit RF signal.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1st input, 2nd input and an output, where the 1st input is operably coupled to receive the high frequency signal. The transistor has a gate, a drain, and a source, where the gate is coupled to the output of the amplifier, the source is coupled to a supply voltage, and the drain is coupled to the 2nd input of the amplifier. The capacitor is operably coupled to the drain of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: A programmable mixer includes a 1st mixing stage, a 2nd mixing stage, a coupling element, and a compensation module. The 1st mixing stage is operably coupled to mix one leg of a differential input signal with a differential local oscillation. The 2nd mixing stage is operably coupled to mix the other leg of the differential input with the differential local oscillation. The coupling element couples the 1st and 2nd mixing stages together. The compensation module is operably coupled to the 1st mixing stage and/or the 2nd mixing stage to modify the operational characteristics (e.g., current, impedance, gain, et cetera) of the 1st and/or 2nd mixing stages based on a control signal.

Abstract: A data slicer for an FSK demodulator employs a peak and valley detector, each of which has a discharge path with selectable decay rates. One of the decay rates is significantly faster than another. The data slicer employs a decay rate selector that selects between the faster and slower decay rates. The data slicer is fed with a frequency-to-voltage converted FSK modulated signal. The faster decay rate for the peak and valley detector outputs is selected when the difference between the current peak and valley voltages exceeds a predetermined percentage (e.g. 75%) of the expected swing of the voltage input (i.e., when there is a DC offset present due to an offset in the carrier frequency of the transmitter). In this mode, the faster decay rate permits faster acquisition of packet data in the presence of DC offset, as it permits the data slicer to converge on an appropriate switching point more quickly.