Abstract: This application relates to the field of lighting, and discloses an LED filament. The LED filament includes an LED chip unit, a light conversion layer, and an electrode. The light conversion layer covers the LED chip unit and part of the electrode, and a color of a light emitted by the LED filament after lighting is different from a color of the light conversion layer. This application has the characteristics of uniform light emission and good heat dissipation effect.

Abstract: The present disclosure provides a P450 cytochrome enzyme for andrographolide synthesis and its application, belonging to the field of bioengineering. The present disclosure uses Saccharomyces cerevisiae CEN.PK2-1D as a host, and implements knockout of ROX1 and GAL80 genes on the genome, and integrative expression of GGPP synthase encoding gene and CPS diterpene synthase encoding gene at ROX1 site; and implements free expression of ApCPR and CYP71A8 and CYP71D10 both with truncated signal peptides, successfully constructing recombinant S. cerevisiae, and achieving de novo synthesis of 3,15,19-Trihydroxy-8(17),13-ent-labdadiene-16-oic acid. Compared with the blank, a response value of a product peak reaches 1.9*106, and this strategy provides necessary reference for analyzing biosynthetic pathway of andrographolide and using metabolic engineering to synthesize andrographolide and related derivatives thereof.

Abstract: A buffer structure includes at least one internal main layer, at least one external main layer, and a rib portion. An inner side of the internal main layer forms an accommodating space, and the external main layer surrounds an outer side of the internal main layer. The rib portion is located between two first folding lines and forms a ring shape. The two first folding lines are parallel to each other. One of the two first folding lines is connected to the internal main layer, and the other one of the two first folding lines is connected to the external main layer. The rib portion is connected between the internal main layer and the external main layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.

Abstract: An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.

Abstract: A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.

Abstract: A supporting structure and a packing box are provided. The supporting structure includes a plate-shaped body that has a first supporting area with at least one first through hole, a second supporting area with at least one second through hole, and a foldable area located between the first supporting area and the second supporting area. The first through hole includes a supporting portion and a passage portion in communication with the supporting portion and the second through hole. The first supporting area and the second supporting area are folded relative to each other along the foldable area so as to form an accommodating space between the first through hole and the second through hole.

Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Abstract: A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.

Abstract: A sample analysis system and method, a sample image analysis system, and a hematology analyzer, the sample analysis system including at least one hematology analyzer, a controller, a first transport device, a sample slide preparation device and a sample image capturing device, wherein one of the hematology analyzers is configured to analyze a first test blood sample of a subject so as to obtain a sample analysis result; the controller is configured to control the first transport device to transport the first blood sample to the sample slide preparation device when the sample analysis result meets a preset condition; the sample slide preparation device is configured to prepare a sample slide of the first blood sample; the sample image capturing device is configured to image a sample region in the sample slide so as to obtain a sample image; and the controller is further configured to generate a retest instruction when the sample image includes information indicating that the first blood sample is an abnormal s

Abstract: A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.

Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

Abstract: Embodiments of the present invention relate to a sample image photographing method and a corresponding sample image photographing apparatus.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes a substrate, a copper layer, an organic composite protective layer, and a silver nanowire layer. The copper layer is disposed on the substrate. The nanowire-distribution-promotion layer is disposed between the copper layer and the silver nanowire layer.

Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes: a substrate; a copper layer disposed on the substrate; an adhesion promotion layer disposed on the copper layer, wherein the adhesion promotion layer forms a monomolecular adsorption layer on the surface of the copper layer; and a silver nanowire layer disposed on the adhesion promotion layer, and the adhesive force between the copper layer and the silver nanowire layer is 3B or more. In the present disclosure, by disposing the adhesion promotion layer on the copper layer, in the stacked structure of the copper layer and the silver nanowire layer, the adhesive force between the copper layer and the silver nanowire layer is increased, so as to prevent a peeling phenomenon of the copper layer occurring in the subsequent yellow-light process.

Abstract: A touch panel has a substrate having a display region and a peripheral region, a touch sensing electrode disposed in the display region of the substrate, and a peripheral circuit disposed in the peripheral region of the substrate. The touch sensing electrode is electrically connected to the peripheral circuit, and the touch sensing electrode layer includes a first portion of a patterned metal nanowire layer. The peripheral circuit includes a patterned conductive layer and a second portion of the metal nanowire layer. At least a non-conductive material of the conductive layer is between the peripheral circuit and a second peripheral circuit.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.