Abstract: A supporting structure and a packing box are provided. The supporting structure includes a plate-shaped body that has a first supporting area with at least one first through hole, a second supporting area with at least one second through hole, and a foldable area located between the first supporting area and the second supporting area. The first through hole includes a supporting portion and a passage portion in communication with the supporting portion and the second through hole. The first supporting area and the second supporting area are folded relative to each other along the foldable area so as to form an accommodating space between the first through hole and the second through hole.

Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Abstract: A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.

Abstract: A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.

Abstract: A sample analysis system and method, a sample image analysis system, and a hematology analyzer, the sample analysis system including at least one hematology analyzer, a controller, a first transport device, a sample slide preparation device and a sample image capturing device, wherein one of the hematology analyzers is configured to analyze a first test blood sample of a subject so as to obtain a sample analysis result; the controller is configured to control the first transport device to transport the first blood sample to the sample slide preparation device when the sample analysis result meets a preset condition; the sample slide preparation device is configured to prepare a sample slide of the first blood sample; the sample image capturing device is configured to image a sample region in the sample slide so as to obtain a sample image; and the controller is further configured to generate a retest instruction when the sample image includes information indicating that the first blood sample is an abnormal s

Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: Embodiments of the present invention relate to a sample image photographing method and a corresponding sample image photographing apparatus.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes a substrate, a copper layer, an organic composite protective layer, and a silver nanowire layer. The copper layer is disposed on the substrate. The nanowire-distribution-promotion layer is disposed between the copper layer and the silver nanowire layer.

Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes: a substrate; a copper layer disposed on the substrate; an adhesion promotion layer disposed on the copper layer, wherein the adhesion promotion layer forms a monomolecular adsorption layer on the surface of the copper layer; and a silver nanowire layer disposed on the adhesion promotion layer, and the adhesive force between the copper layer and the silver nanowire layer is 3B or more. In the present disclosure, by disposing the adhesion promotion layer on the copper layer, in the stacked structure of the copper layer and the silver nanowire layer, the adhesive force between the copper layer and the silver nanowire layer is increased, so as to prevent a peeling phenomenon of the copper layer occurring in the subsequent yellow-light process.

Abstract: A touch panel has a substrate having a display region and a peripheral region, a touch sensing electrode disposed in the display region of the substrate, and a peripheral circuit disposed in the peripheral region of the substrate. The touch sensing electrode is electrically connected to the peripheral circuit, and the touch sensing electrode layer includes a first portion of a patterned metal nanowire layer. The peripheral circuit includes a patterned conductive layer and a second portion of the metal nanowire layer. At least a non-conductive material of the conductive layer is between the peripheral circuit and a second peripheral circuit.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.

Abstract: A semiconductor structure includes two circuit regions and two inner seal rings, each of which surrounds one of the circuit regions. Each inner seal ring has a substantially rectangular periphery with four interior corner stress relief (CSR) structures. The semiconductor structure further includes an outer seal ring surrounding the two inner seal rings. The outer seal ring has a substantially rectangular periphery without CSR structures at four interior corners of the outer seal ring. The outer seal ring includes a plurality of first fin structures located between each of the two inner seal rings and a respective short side of the outer seal ring. Each first fin structure is parallel with the respective short side of the outer seal ring. Lengths of the first fin structures gradually decrease along a direction from the inner seal rings to the respective short side of the outer seal ring.

Abstract: A sample analysis system, method and a cell image analysis device. The sample analysis system includes a blood cell analyzer, a smear preparation apparatus, a cell image analysis apparatus, and a controller. The controller obtains a test result of at least one sample from the blood cell analyzer. When one sample needs to be analyzed by the cell image analysis device, the controller can further control an imaging condition used by the cell image analysis device according to a value of at least one type of cells in the test result of the sample, such that the cell image analysis device can automatically selects an imaging condition matching the test result for imaging according to different test results of the sample. Therefore, a matching imaging condition is used to specifically capture and analyze cell images of a smear of the sample, thereby improving processing efficiency and accuracy.

Abstract: Provided are cell image analysis devices and sample analysis methods. A sample smear of a test sample is imaged by an imaging device in an assigned analysis mode to obtain first cell images of the test sample, which are identified and analyzed by a control device. If it is identified that there is preset abnormality in the sample smear, an analysis mode different from the assigned analysis mode and corresponding to the present abnormality is determined as an additional analysis mode, and the imaging device is controlled to image the sample smear in the additional analysis mode. The additional analysis mode matches with the preset abnormality, so that the imaging device is allowed to obtain cell images in the additional analysis mode, to identify and analyze the cell images matching the preset abnormality, thereby increasing processing efficiency and accuracy of processing result.

Abstract: A device for analyzing cell morphology and a method for identifying cells are provided. A digital camera photographs a cell image of a blood sample under a low-magnification objective lens. A processor identifies and positions suspected cells of preset type in the cell image to obtain an identification result. Based on the identification result and a target number, the processor determines a number of suspected cells of preset type to be identified and positioned under the low-magnification objective lens. The digital camera further photographs, under a high-magnification objective lens, the suspected cells of preset type identified and positioned, and then the processor identifies whether the suspected cells of preset type photographed are cells of preset type, to count the number of cells of preset type photographed under the high-magnification objective lens and obtain a statistical value. If the statistical value?the target number, photographing is stopped.

Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes a substrate, a copper layer, an organic composite protective layer, and a silver nanowire layer. The copper layer is disposed on the substrate. The nanowire-distribution-promotion layer is disposed between the copper layer and the silver nanowire layer.