Patents by Inventor Shang-Chih Hsieh

Shang-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11544437
    Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Chun-Fu Chen, Ting-Wei Chiang, Hui-Zhong Zhuang, Hsiang-Jen Tseng
  • Publication number: 20220382951
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Lee-Chung LU, Li-Chun TIEN, Meng-Hung SHEN, Shang-Chih HSIEH, Chi-Yu LU
  • Patent number: 11509306
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Greg Gruber, Chi-Lin Liu, Ming-Chang Kuo, Lee-Chung Lu, Shang-Chih Hsieh
  • Publication number: 20220368318
    Abstract: A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Kai-Chi HUANG, Yung-Chen CHIEN, Chi-Lin LIU, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
  • Publication number: 20220360253
    Abstract: A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Huaixin XIAN, Qingchao MENG, Yang ZHOU, Shang-Chih HSIEH
  • Publication number: 20220334842
    Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kai-Chi Huang, Chi-Lin Liu, Wei-Hsiang Ma, Shang-Chih Hsieh
  • Publication number: 20220327275
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Patent number: 11469743
    Abstract: An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: October 11, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Qingchao Meng, Yang Zhou, Shang-Chih Hsieh
  • Publication number: 20220321108
    Abstract: An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.
    Type: Application
    Filed: April 29, 2021
    Publication date: October 6, 2022
    Inventors: Huaixin XIAN, Qingchao MENG, Yang ZHOU, Shang-Chih HSIEH
  • Publication number: 20220321126
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
    Type: Application
    Filed: June 8, 2022
    Publication date: October 6, 2022
    Inventors: Yu-Lun OU, Ji-Yung LIN, Yung-Chen CHIEN, Ruei-Wun SUN, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
  • Patent number: 11461528
    Abstract: An integrated circuit structure includes a first, a second and a third set of conductive structures and a first and a second set of vias. The first set of conductive structures extend in a first direction, and is located at a first level. The second set of conductive structures extends in a second direction, overlaps the first set of conductive structures, and is located at a second level. The first set of vias is between, and electrically couples the first and the second set of conductive structures. The third set of conductive structures extends in the first direction, overlaps the second set of conductive structures, covers a portion of the first set of conductive structures, and is located at a third level. The second set of vias is between, and electrically couples the second and the third set of conductive structures.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Patent number: 11456728
    Abstract: A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chi Huang, Yung-Chen Chien, Chi-Lin Liu, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
  • Patent number: 11422819
    Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kai-Chi Huang, Chi-Lin Liu, Wei-Hsiang Ma, Shang-Chih Hsieh
  • Patent number: 11392743
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Patent number: 11387818
    Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Patent number: 11362660
    Abstract: A circuit includes a level shifter circuit, an output circuit, an enable circuit, a first and a second feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to generate at least a first and a second signal responsive to at least the first enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, and configured to receive the first and the second signal. The enable circuit is configured to generate a second enable signal responsive to the first enable signal. The first feedback circuit is configured to receive the first enable signal, the second enable signal and the first feedback signal. The second feedback circuit is configured to receive the first enable signal, the second enable signal and the second feedback signal.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
  • Patent number: 11270052
    Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Jerry Chang Jui Kao, Chi-Lin Liu, Cheng-Chung Lin, Shang-Chih Hsieh
  • Publication number: 20210389952
    Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Kai-Chi HUANG, Chi-Lin LIU, Wei-Hsiang MA, Shang-Chih HSIEH
  • Publication number: 20210376819
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Shao-Yu Steve Wang, Chien-Te Wu, Shang-Chih Hsieh, Nick Tsai
  • Publication number: 20210344330
    Abstract: A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH