Patents by Inventor Shang-Chih Hsieh

Shang-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530345
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Publication number: 20190363701
    Abstract: A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on at least a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have a first voltage swing or a second voltage swing based on the first output signal and the second output signal. The first voltage swing is different from the second voltage swing.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Chi-Lin LIU, Shang-Chih HSIEH, Lee-Chung LU, Chang-Yu WU
  • Patent number: 10483950
    Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Publication number: 20190332736
    Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 31, 2019
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Publication number: 20190319624
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 17, 2019
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Publication number: 20190305761
    Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.
    Type: Application
    Filed: March 6, 2019
    Publication date: October 3, 2019
    Inventors: Kai-Chi HUANG, Jerry Chang Jui KAO, Chi-Lin LIU, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA, Yung-Chen CHIEN
  • Publication number: 20190280678
    Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The output stage is configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal, wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 12, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
  • Publication number: 20190258768
    Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Patent number: 10380306
    Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10382018
    Abstract: A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have different voltage swings based on the first output signal and the second output signal. The trigger circuit includes a logic circuit coupled to at least the first latch or the second latch. The logic circuit is configured to output the second output signal.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Lee-Chung Lu, Chang-Yu Wu
  • Publication number: 20190229715
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Publication number: 20190173456
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Inventors: Ta-Pen GUO, Chi-Lin LIU, Shang-Chih HSIEH, Jerry Chang-Jui KAO, Li-Chun TIEN, Lee-Chung LU
  • Patent number: 10291210
    Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Patent number: 10289789
    Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10270430
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang-Jui Kao, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 10270432
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Publication number: 20190115905
    Abstract: A device is disclosed that includes a level shifter and a selector. The level shifter is configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and is configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level. The selector is coupled to the first output terminal and the second output terminal. The selector is configured to pass one of the first output signal or the second output signal in response to the first input signal, to an output of the selector.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
  • Publication number: 20190102503
    Abstract: A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Lee-Chung LU, Li-Chun TIEN, Meng-Hung SHEN, Shang-Chih HSIEH, Chi-Yu LU
  • Patent number: 10164615
    Abstract: A device is disclosed that includes a level shifter and an output stage. The level shifter includes a first current limiter. The level shifter is configured to generate a first output signal at a first terminal of the first current limiter, and to generate a second output signal at a second terminal of the first current limiter according to a first input signal. The output stage is configured to adjust a voltage swing of a selected one of the first output signal and the second output signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
  • Publication number: 20180336293
    Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.
    Type: Application
    Filed: March 27, 2018
    Publication date: November 22, 2018
    Inventors: Chi-Lin LIU, Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA